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Searched refs:gpu_read (Results 1 – 25 of 27) sorted by relevance

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/linux-6.12.1/drivers/gpu/drm/panfrost/
Dpanfrost_gpu.c30 fault_status = gpu_read(pfdev, GPU_FAULT_STATUS); in panfrost_gpu_irq_handler()
31 state = gpu_read(pfdev, GPU_INT_STAT); in panfrost_gpu_irq_handler()
36 u64 address = (u64) gpu_read(pfdev, GPU_FAULT_ADDRESS_HI) << 32; in panfrost_gpu_irq_handler()
37 address |= gpu_read(pfdev, GPU_FAULT_ADDRESS_LO); in panfrost_gpu_irq_handler()
146 quirks = gpu_read(pfdev, GPU_TILER_CONFIG); in panfrost_gpu_init_quirks()
251 pfdev->features.l2_features = gpu_read(pfdev, GPU_L2_FEATURES); in panfrost_gpu_init_features()
252 pfdev->features.core_features = gpu_read(pfdev, GPU_CORE_FEATURES); in panfrost_gpu_init_features()
253 pfdev->features.tiler_features = gpu_read(pfdev, GPU_TILER_FEATURES); in panfrost_gpu_init_features()
254 pfdev->features.mem_features = gpu_read(pfdev, GPU_MEM_FEATURES); in panfrost_gpu_init_features()
255 pfdev->features.mmu_features = gpu_read(pfdev, GPU_MMU_FEATURES); in panfrost_gpu_init_features()
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Dpanfrost_dump.c97 dumpreg->value = gpu_read(pfdev, reg); in panfrost_core_dump_registers()
Dpanfrost_regs.h336 #define gpu_read(dev, reg) readl(dev->iomem + reg) macro
/linux-6.12.1/drivers/gpu/drm/panthor/
Dpanthor_gpu.c87 ptdev->gpu_info.gpu_id = gpu_read(ptdev, GPU_ID); in panthor_gpu_init_info()
88 ptdev->gpu_info.csf_id = gpu_read(ptdev, GPU_CSF_ID); in panthor_gpu_init_info()
89 ptdev->gpu_info.gpu_rev = gpu_read(ptdev, GPU_REVID); in panthor_gpu_init_info()
90 ptdev->gpu_info.core_features = gpu_read(ptdev, GPU_CORE_FEATURES); in panthor_gpu_init_info()
91 ptdev->gpu_info.l2_features = gpu_read(ptdev, GPU_L2_FEATURES); in panthor_gpu_init_info()
92 ptdev->gpu_info.tiler_features = gpu_read(ptdev, GPU_TILER_FEATURES); in panthor_gpu_init_info()
93 ptdev->gpu_info.mem_features = gpu_read(ptdev, GPU_MEM_FEATURES); in panthor_gpu_init_info()
94 ptdev->gpu_info.mmu_features = gpu_read(ptdev, GPU_MMU_FEATURES); in panthor_gpu_init_info()
95 ptdev->gpu_info.thread_features = gpu_read(ptdev, GPU_THREAD_FEATURES); in panthor_gpu_init_info()
96 ptdev->gpu_info.max_threads = gpu_read(ptdev, GPU_THREAD_MAX_THREADS); in panthor_gpu_init_info()
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Dpanthor_device.h294 if (!gpu_read(ptdev, __reg_prefix ## _INT_STAT)) \
308 u32 status = gpu_read(ptdev, __reg_prefix ## _INT_RAWSTAT) & pirq->mask; \
Dpanthor_regs.h236 #define gpu_read(dev, reg) \ macro
Dpanthor_fw.c993 !(gpu_read(ptdev, JOB_INT_STAT) & JOB_INT_GLOBAL_IF)) in panthor_fw_start()
1004 u32 status = gpu_read(ptdev, MCU_STATUS); in panthor_fw_start()
/linux-6.12.1/drivers/gpu/drm/msm/adreno/
Da5xx_gpu.c1021 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(i))); in a5xx_recover()
1028 gpu_read(gpu, REG_A5XX_RBBM_SW_RESET_CMD); in a5xx_recover()
1068 if (gpu_read(gpu, REG_A5XX_RBBM_STATUS) & ~A5XX_RBBM_STATUS_HI_BUSY) in _a5xx_check_idle()
1075 return !(gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS) & in _a5xx_check_idle()
1096 gpu_read(gpu, REG_A5XX_RBBM_STATUS), in a5xx_idle()
1097 gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS), in a5xx_idle()
1098 gpu_read(gpu, REG_A5XX_CP_RB_RPTR), in a5xx_idle()
1099 gpu_read(gpu, REG_A5XX_CP_RB_WPTR)); in a5xx_idle()
1112 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(4)), in a5xx_fault_handler()
1113 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(5)), in a5xx_fault_handler()
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Da2xx_gpu.c274 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a2xx_recover()
282 gpu_read(gpu, REG_A2XX_RBBM_SOFT_RESET); in a2xx_recover()
306 if (spin_until(!(gpu_read(gpu, REG_A2XX_RBBM_STATUS) & in a2xx_idle()
321 mstatus = gpu_read(gpu, REG_A2XX_MASTER_INT_SIGNAL); in a2xx_irq()
324 status = gpu_read(gpu, REG_A2XX_MH_INTERRUPT_STATUS); in a2xx_irq()
328 gpu_read(gpu, REG_A2XX_MH_MMU_PAGE_FAULT)); in a2xx_irq()
334 status = gpu_read(gpu, REG_AXXX_CP_INT_STATUS); in a2xx_irq()
344 status = gpu_read(gpu, REG_A2XX_RBBM_INT_STATUS); in a2xx_irq()
451 gpu_read(gpu, REG_A2XX_RBBM_STATUS)); in a2xx_dump()
464 state->rbbm_status = gpu_read(gpu, REG_A2XX_RBBM_STATUS); in a2xx_gpu_state_get()
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Da6xx_gpu.c29 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & in _a6xx_check_idle()
33 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & in _a6xx_check_idle()
46 gpu_read(gpu, REG_A6XX_RBBM_STATUS), in a6xx_idle()
47 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), in a6xx_idle()
48 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), in a6xx_idle()
49 gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); in a6xx_idle()
459 val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); in a6xx_set_hwcg()
879 gpu_read(gpu, REG_A6XX_GBIF_HALT); in hw_init()
882 gpu_read(gpu, REG_A6XX_RBBM_GPR0_CNTL); in hw_init()
885 gpu_read(gpu, REG_A6XX_GBIF_HALT); in hw_init()
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Da4xx_gpu.c277 val = gpu_read(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ); in a4xx_hw_init()
358 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a4xx_recover()
366 gpu_read(gpu, REG_A4XX_RBBM_SW_RESET_CMD); in a4xx_recover()
392 if (spin_until(!(gpu_read(gpu, REG_A4XX_RBBM_STATUS) & in a4xx_idle()
406 status = gpu_read(gpu, REG_A4XX_RBBM_INT_0_STATUS); in a4xx_irq()
410 uint32_t reg = gpu_read(gpu, REG_A4XX_CP_PROTECT_STATUS); in a4xx_irq()
560 state->rbbm_status = gpu_read(gpu, REG_A4XX_RBBM_STATUS); in a4xx_gpu_state_get()
568 gpu_read(gpu, REG_A4XX_RBBM_STATUS)); in a4xx_dump()
586 reg = gpu_read(gpu, REG_A4XX_RBBM_POWER_STATUS); in a4xx_pm_resume()
626 ring->memptrs->rptr = gpu_read(gpu, REG_A4XX_CP_RB_RPTR); in a4xx_get_rptr()
Da5xx_debugfs.c23 gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA)); in pfp_print()
36 gpu_read(gpu, REG_A5XX_CP_ME_STAT_DATA)); in me_print()
49 gpu_read(gpu, REG_A5XX_CP_MEQ_DBG_DATA)); in meq_print()
64 val[j] = gpu_read(gpu, REG_A5XX_CP_ROQ_DBG_DATA); in roq_print()
Da3xx_gpu.c374 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a3xx_recover()
382 gpu_read(gpu, REG_A3XX_RBBM_SW_RESET_CMD); in a3xx_recover()
408 if (spin_until(!(gpu_read(gpu, REG_A3XX_RBBM_STATUS) & in a3xx_idle()
423 status = gpu_read(gpu, REG_A3XX_RBBM_INT_0_STATUS); in a3xx_irq()
477 gpu_read(gpu, REG_A3XX_RBBM_STATUS)); in a3xx_dump()
490 state->rbbm_status = gpu_read(gpu, REG_A3XX_RBBM_STATUS); in a3xx_gpu_state_get()
507 ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR); in a3xx_get_rptr()
Da6xx_gpu_state.c188 data[0] = gpu_read(gpu, REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2); in debugbus_read()
189 data[1] = gpu_read(gpu, REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1); in debugbus_read()
231 data[i] = gpu_read(gpu, REG_A6XX_VBIF_TEST_BUS_OUT); in vbif_debugbus_read()
261 clk = gpu_read(gpu, REG_A6XX_VBIF_CLKON); in a6xx_get_vbif_debugbus_block()
1132 obj->data[index++] = gpu_read(gpu, in a6xx_get_ahb_gpu_registers()
1157 obj->data[index++] = gpu_read(gpu, regs[i] + j); in a7xx_get_ahb_gpu_registers()
1422 return gpu_read(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2) >> 14; in a6xx_get_cp_roq_size()
1434 return 4 * (gpu_read(gpu, REG_A6XX_CP_SQE_UCODE_DBG_DATA) >> 20); in a7xx_get_cp_roq_size()
1460 obj->data[i] = gpu_read(gpu, indexed->data); in a6xx_get_indexed_regs()
1482 val = gpu_read(gpu, REG_A6XX_CP_CHICKEN_DBG); in a6xx_get_indexed_registers()
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Da5xx_gpu.h145 if ((gpu_read(gpu, reg) & mask) == value) in spin_usecs()
Da5xx_power.c267 u32 val = gpu_read(gpu, REG_A5XX_GPMU_GENERAL_1); in a5xx_gpmu_init()
Da5xx_preempt.c193 status = gpu_read(gpu, REG_A5XX_CP_CONTEXT_SWITCH_CNTL); in a5xx_preempt_irq()
Dadreno_gpu.c723 state->registers[pos++] = gpu_read(gpu, addr); in adreno_gpu_state_get()
961 uint32_t val = gpu_read(gpu, addr); in adreno_dump()
/linux-6.12.1/drivers/gpu/drm/etnaviv/
Detnaviv_gpu.c191 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); in etnaviv_hw_specs()
192 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); in etnaviv_hw_specs()
193 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); in etnaviv_hw_specs()
194 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); in etnaviv_hw_specs()
338 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); in etnaviv_hw_identify()
346 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); in etnaviv_hw_identify()
348 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); in etnaviv_hw_identify()
349 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); in etnaviv_hw_identify()
350 gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID); in etnaviv_hw_identify()
357 gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID); in etnaviv_hw_identify()
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Detnaviv_perfmon.c46 return gpu_read(gpu, domain->profile_read); in perf_reg_read()
61 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in pipe_perf_reg_read()
80 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in pipe_reg_read()
86 value += gpu_read(gpu, signal->data); in pipe_reg_read()
106 return gpu_read(gpu, reg); in hi_total_cycle_read()
120 return gpu_read(gpu, reg); in hi_total_idle_cycle_read()
Detnaviv_iommu_v2.c172 if (gpu_read(gpu, VIVS_MMUv2_CONTROL) & VIVS_MMUv2_CONTROL_ENABLE) in etnaviv_iommuv2_restore_nonsec()
196 if (gpu_read(gpu, VIVS_MMUv2_SEC_CONTROL) & VIVS_MMUv2_SEC_CONTROL_ENABLE) in etnaviv_iommuv2_restore_sec()
Detnaviv_sched.c53 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in etnaviv_sched_timedout_job()
Detnaviv_gpu.h172 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg) in gpu_read() function
Detnaviv_dump.c94 reg->value = cpu_to_le32(gpu_read(gpu, read_addr)); in etnaviv_core_dump_registers()
/linux-6.12.1/drivers/gpu/drm/msm/
Dmsm_gpu.h570 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg) in gpu_read() function

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