29 	if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) &  in _a6xx_check_idle()
33 	return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) &  in _a6xx_check_idle()
46 			gpu_read(gpu, REG_A6XX_RBBM_STATUS),  in a6xx_idle()
47 			gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS),  in a6xx_idle()
48 			gpu_read(gpu, REG_A6XX_CP_RB_RPTR),  in a6xx_idle()
49 			gpu_read(gpu, REG_A6XX_CP_RB_WPTR));  in a6xx_idle()
459 	val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL);  in a6xx_set_hwcg()
879 		gpu_read(gpu, REG_A6XX_GBIF_HALT);  in hw_init()
882 		gpu_read(gpu, REG_A6XX_RBBM_GPR0_CNTL);  in hw_init()
885 		gpu_read(gpu, REG_A6XX_GBIF_HALT);  in hw_init()
888 		gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT);  in hw_init()
1220 			gpu_read(gpu, REG_A6XX_RBBM_STATUS));  in a6xx_dump()
1235 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i)));  in a6xx_recover()
1320 	val = gpu_read(gpu, REG_A6XX_UCHE_CLIENT_PF);  in a6xx_uche_fault_block()
1422 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),  in a6xx_fault_handler()
1423 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),  in a6xx_fault_handler()
1424 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),  in a6xx_fault_handler()
1425 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)),  in a6xx_fault_handler()
1436 	u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS);  in a6xx_cp_hw_err_irq()
1442 		val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA);  in a6xx_cp_hw_err_irq()
1454 			gpu_read(gpu, REG_A6XX_CP_HW_FAULT));  in a6xx_cp_hw_err_irq()
1457 		u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS);  in a6xx_cp_hw_err_irq()
1488 	if (gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT)  in a6xx_fault_detect_irq()
1501 		gpu_read(gpu, REG_A6XX_RBBM_STATUS),  in a6xx_fault_detect_irq()
1502 		gpu_read(gpu, REG_A6XX_CP_RB_RPTR),  in a6xx_fault_detect_irq()
1503 		gpu_read(gpu, REG_A6XX_CP_RB_WPTR),  in a6xx_fault_detect_irq()
1505 		gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE),  in a6xx_fault_detect_irq()
1507 		gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE));  in a6xx_fault_detect_irq()
1519 	status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);  in a7xx_sw_fuse_violation_irq()
1539 	u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS);  in a6xx_irq()
1770 		spin_until((gpu_read(gpu, REG_A6XX_RBBM_VBIF_GX_RESET_STATUS) &  in a6xx_bus_clear_pending_transactions()
1774 		spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) &  in a6xx_bus_clear_pending_transactions()
1784 		spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & 1);  in a6xx_bus_clear_pending_transactions()
1789 	spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &  in a6xx_bus_clear_pending_transactions()
1794 	spin_until((gpu_read(gpu,  REG_A6XX_GBIF_HALT_ACK) &  in a6xx_bus_clear_pending_transactions()
1809 	gpu_read(gpu, REG_A6XX_RBBM_SW_RESET_CMD);  in a6xx_gpu_sw_reset()
2079 	return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR);  in a6xx_get_rptr()
2087 		.ib1_rem  = gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE),  in a6xx_progress()
2088 		.ib2_rem  = gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE),  in a6xx_progress()
2105 	cp_state.ib1_rem += gpu_read(gpu, REG_A6XX_CP_ROQ_AVAIL_IB1) >> 16;  in a6xx_progress()
2106 	cp_state.ib2_rem += gpu_read(gpu, REG_A6XX_CP_ROQ_AVAIL_IB2) >> 16;  in a6xx_progress()