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Searched refs:XE_REG (Results 1 – 21 of 21) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/xe/regs/
Dxe_engine_regs.h46 #define RING_TAIL(base) XE_REG((base) + 0x30)
49 #define RING_HEAD(base) XE_REG((base) + 0x34)
52 #define RING_START(base) XE_REG((base) + 0x38)
54 #define RING_CTL(base) XE_REG((base) + 0x3c)
58 #define RING_START_UDW(base) XE_REG((base) + 0x48)
60 #define RING_PSMI_CTL(base) XE_REG((base) + 0x50, XE_REG_OPTION_MASKED)
65 #define RING_PWRCTX_MAXCNT(base) XE_REG((base) + 0x54)
68 #define RING_ACTHD_UDW(base) XE_REG((base) + 0x5c)
69 #define RING_DMA_FADD_UDW(base) XE_REG((base) + 0x60)
70 #define RING_IPEHR(base) XE_REG((base) + 0x68)
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Dxe_gt_regs.h20 #define MTL_MIRROR_TARGET_WP1 XE_REG(0xc60)
25 #define RPM_CONFIG0 XE_REG(0xd00)
33 #define FORCEWAKE_ACK_MEDIA_VDBOX(n) XE_REG(0xd50 + (n) * 4)
34 #define FORCEWAKE_ACK_MEDIA_VEBOX(n) XE_REG(0xd70 + (n) * 4)
35 #define FORCEWAKE_ACK_RENDER XE_REG(0xd84)
37 #define GMD_ID XE_REG(0xd8c)
42 #define FORCEWAKE_ACK_GSC XE_REG(0xdf8)
43 #define FORCEWAKE_ACK_GT_MTL XE_REG(0xdfc)
45 #define MCFG_MCR_SELECTOR XE_REG(0xfd0)
46 #define MTL_MCR_SELECTOR XE_REG(0xfd4)
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Dxe_guc_regs.h16 #define DIST_DBS_POPULATED XE_REG(0xd08)
20 #define DRBREGL(x) XE_REG(0x1000 + (x) * 8)
22 #define DRBREGU(x) XE_REG(0x1000 + (x) * 8 + 4)
24 #define GTCR XE_REG(0x4274)
27 #define GUC_ARAT_C6DIS XE_REG(0xa178)
29 #define GUC_STATUS XE_REG(0xc000)
43 #define GUC_HEADER_INFO XE_REG(0xc014)
45 #define GUC_WOPCM_SIZE XE_REG(0xc050)
49 #define GUC_SHIM_CONTROL XE_REG(0xc064)
60 #define SOFT_SCRATCH(n) XE_REG(0xc180 + (n) * 4)
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Dxe_oa_regs.h9 #define RPM_CONFIG1 XE_REG(0xd04)
12 #define EU_PERF_CNTL0 XE_REG(0xe458)
13 #define EU_PERF_CNTL4 XE_REG(0xe45c)
14 #define EU_PERF_CNTL1 XE_REG(0xe558)
15 #define EU_PERF_CNTL5 XE_REG(0xe55c)
16 #define EU_PERF_CNTL2 XE_REG(0xe658)
17 #define EU_PERF_CNTL6 XE_REG(0xe65c)
18 #define EU_PERF_CNTL3 XE_REG(0xe758)
20 #define OA_TLB_INV_CR XE_REG(0xceec)
23 #define OAR_OACONTROL XE_REG(0x2960)
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Dxe_regs.h10 #define TIMESTAMP_OVERRIDE XE_REG(0x44074)
18 #define GU_CNTL_PROTECTED XE_REG(0x10100C)
21 #define GU_CNTL XE_REG(0x101010)
25 #define XEHP_CLOCK_GATE_DIS XE_REG(0x101014)
28 #define GU_DEBUG XE_REG(0x101018)
31 #define VIRTUAL_CTRL_REG XE_REG(0x10108c)
34 #define XEHP_MTCFG_ADDR XE_REG(0x101800)
37 #define GGC XE_REG(0x108040)
41 #define DSMBASE XE_REG(0x1080C0)
44 #define GSMBASE XE_REG(0x108100)
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Dxe_pcode_regs.h15 #define PVC_GT0_PACKAGE_ENERGY_STATUS XE_REG(0x281004)
16 #define PVC_GT0_PACKAGE_RAPL_LIMIT XE_REG(0x281008)
17 #define PVC_GT0_PACKAGE_POWER_SKU_UNIT XE_REG(0x281068)
18 #define PVC_GT0_PLATFORM_ENERGY_STATUS XE_REG(0x28106c)
19 #define PVC_GT0_PACKAGE_POWER_SKU XE_REG(0x281080)
21 #define BMG_PACKAGE_POWER_SKU XE_REG(0x138098)
22 #define BMG_PACKAGE_POWER_SKU_UNIT XE_REG(0x1380dc)
23 #define BMG_PACKAGE_ENERGY_STATUS XE_REG(0x138120)
24 #define BMG_PACKAGE_RAPL_LIMIT XE_REG(0x138440)
25 #define BMG_PLATFORM_ENERGY_STATUS XE_REG(0x138458)
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Dxe_gsc_regs.h19 #define HECI_H_CSR(base) XE_REG((base) + 0x4)
30 #define HECI_FWSTS1(base) XE_REG((base) + 0xc40)
35 #define HECI_FWSTS2(base) XE_REG((base) + 0xc48)
36 #define HECI_FWSTS3(base) XE_REG((base) + 0xc60)
37 #define HECI_FWSTS4(base) XE_REG((base) + 0xc64)
38 #define HECI_FWSTS5(base) XE_REG((base) + 0xc68)
40 #define HECI_FWSTS6(base) XE_REG((base) + 0xc6c)
42 #define HECI_H_GS1(base) XE_REG((base) + 0xc4c)
45 #define GSCI_TIMER_STATUS XE_REG(0x11ca28)
Dxe_mchbar_regs.h21 #define PCU_CR_PACKAGE_POWER_SKU XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5930)
30 #define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
35 #define PCU_CR_PACKAGE_ENERGY_STATUS XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x593c)
37 #define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
Dxe_reg_defs.h112 #define XE_REG(r_, ...) ((const struct xe_reg)XE_REG_INITIALIZER(r_, ##__VA_ARGS__)) macro
/linux-6.12.1/drivers/gpu/drm/xe/compat-i915-headers/
Dintel_uncore.h30 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in intel_uncore_read()
38 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in intel_uncore_read8()
46 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in intel_uncore_read16()
55 struct xe_reg lower_reg = XE_REG(i915_mmio_reg_offset(i915_lower_reg)); in intel_uncore_read64_2x32()
56 struct xe_reg upper_reg = XE_REG(i915_mmio_reg_offset(i915_upper_reg)); in intel_uncore_read64_2x32()
73 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in intel_uncore_posting_read()
81 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in intel_uncore_write()
89 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in intel_uncore_rmw()
98 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in intel_wait_for_register()
108 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in intel_wait_for_register_fw()
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/linux-6.12.1/drivers/gpu/drm/xe/
Dxe_pcode_api.h10 #define PCODE_MAILBOX XE_REG(0x138124)
25 #define PCODE_DATA0 XE_REG(0x138128)
26 #define PCODE_DATA1 XE_REG(0x13812C)
Dxe_reg_whitelist.c18 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
49 XE_RTP_ACTIONS(WHITELIST(XE_REG(0x4400),
52 WHITELIST(XE_REG(0x4500),
Dxe_pat.c161 struct xe_reg reg = XE_REG(_PAT_INDEX(i)); in program_pat()
189 u32 pat = xe_mmio_read32(gt, XE_REG(_PAT_INDEX(i))); in xelp_dump()
281 pat = xe_mmio_read32(gt, XE_REG(_PAT_INDEX(i))); in xelpg_dump()
319 xe_mmio_write32(gt, XE_REG(_PAT_ATS), xe2_pat_ats.value); in xe2lpm_program_pat()
322 xe_mmio_write32(gt, XE_REG(_PAT_PTA), xe2_pat_pta.value); in xe2lpm_program_pat()
339 pat = xe_mmio_read32(gt, XE_REG(_PAT_INDEX(i))); in xe2_dump()
358 pat = xe_mmio_read32(gt, XE_REG(_PAT_PTA)); in xe2_dump()
Dxe_tuning.c16 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
Dxe_irq.c29 #define IMR(offset) XE_REG(offset + 0x4)
30 #define IIR(offset) XE_REG(offset + 0x8)
31 #define IER(offset) XE_REG(offset + 0xc)
Dxe_guc_pc.c34 #define RP_STATE_CAP XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5998)
39 #define FREQ_INFO_REC XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)
42 #define GT_PERF_STATUS XE_REG(0x1381b4)
Dxe_gt_mcr.c49 #define STEER_SEMAPHORE XE_REG(0xFD0)
Dxe_hwmon.c136 return XE_REG(0); in xe_hwmon_get_reg()
Dxe_wa.c95 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
Dxe_oa.c2035 oa_regs[i].addr = XE_REG(addr); in xe_oa_alloc_regs()
/linux-6.12.1/drivers/gpu/drm/xe/tests/
Dxe_rtp_test.c23 #define REGULAR_REG1 XE_REG(1)
24 #define REGULAR_REG2 XE_REG(2)
25 #define REGULAR_REG3 XE_REG(3)
29 #define MASKED_REG1 XE_REG(1, XE_REG_OPTION_MASKED)
32 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)