/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
D | gfx_v6_0.c | 87 #define NUM_BANKS(x) ((x) << 20) macro 411 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init() 419 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init() 427 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init() 434 NUM_BANKS(ADDR_SURF_8_BANK) | in gfx_v6_0_tiling_mode_table_init() 446 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init() 454 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init() 462 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init() 474 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init() 482 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init() [all …]
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D | gfx_v8_0.c | 76 #define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT) macro 2194 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init() 2198 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init() 2202 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init() 2206 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init() 2210 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init() 2214 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init() 2218 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init() 2222 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v8_0_tiling_mode_table_init() 2226 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v8_0_tiling_mode_table_init() [all …]
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D | gfx_v7_0.c | 1122 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v7_0_tiling_mode_table_init() 1126 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v7_0_tiling_mode_table_init() 1130 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v7_0_tiling_mode_table_init() 1134 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v7_0_tiling_mode_table_init() 1138 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v7_0_tiling_mode_table_init() 1142 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v7_0_tiling_mode_table_init() 1146 NUM_BANKS(ADDR_SURF_4_BANK)); in gfx_v7_0_tiling_mode_table_init() 1150 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v7_0_tiling_mode_table_init() 1154 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v7_0_tiling_mode_table_init() 1158 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v7_0_tiling_mode_table_init() [all …]
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D | cikd.h | 197 # define NUM_BANKS(x) ((x) << 6) macro
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D | sdma_v4_4_2.c | 163 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4); in sdma_v4_4_2_inst_init_golden_registers() 169 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS, in sdma_v4_4_2_inst_init_golden_registers()
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D | sid.h | 1218 # define NUM_BANKS(x) ((x) << 20) macro
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D | dce_v6_0.c | 1963 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v6_0_crtc_do_set_base()
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D | dce_v8_0.c | 1932 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v8_0_crtc_do_set_base()
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D | dce_v10_0.c | 1993 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v10_0_crtc_do_set_base()
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D | dce_v11_0.c | 2043 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v11_0_crtc_do_set_base()
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D | gfx_v9_4_3.c | 959 NUM_BANKS); in gfx_v9_4_3_gpu_early_init()
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D | gfx_v9_0.c | 2116 NUM_BANKS); in gfx_v9_0_gpu_early_init()
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/linux-6.12.1/drivers/gpu/drm/radeon/ |
D | si.c | 2500 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init() 2509 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init() 2518 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init() 2527 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init() 2536 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init() 2545 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init() 2554 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init() 2563 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init() 2572 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init() 2581 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init() [all …]
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D | cik.c | 2439 NUM_BANKS(ADDR_SURF_16_BANK)); in cik_tiling_mode_table_init() 2443 NUM_BANKS(ADDR_SURF_16_BANK)); in cik_tiling_mode_table_init() 2447 NUM_BANKS(ADDR_SURF_16_BANK)); in cik_tiling_mode_table_init() 2451 NUM_BANKS(ADDR_SURF_16_BANK)); in cik_tiling_mode_table_init() 2455 NUM_BANKS(ADDR_SURF_8_BANK)); in cik_tiling_mode_table_init() 2459 NUM_BANKS(ADDR_SURF_4_BANK)); in cik_tiling_mode_table_init() 2463 NUM_BANKS(ADDR_SURF_2_BANK)); in cik_tiling_mode_table_init() 2467 NUM_BANKS(ADDR_SURF_16_BANK)); in cik_tiling_mode_table_init() 2471 NUM_BANKS(ADDR_SURF_16_BANK)); in cik_tiling_mode_table_init() 2475 NUM_BANKS(ADDR_SURF_16_BANK)); in cik_tiling_mode_table_init() [all …]
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D | sid.h | 1221 # define NUM_BANKS(x) ((x) << 20) macro
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D | cikd.h | 1275 # define NUM_BANKS(x) ((x) << 6) macro
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubp/dcn10/ |
D | dcn10_hubp.h | 269 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\ 467 type NUM_BANKS;\
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D | dcn10_hubp.c | 150 NUM_BANKS, log_2(info->gfx9.num_banks), in hubp1_program_tiling()
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/linux-6.12.1/drivers/gpu/drm/amd/display/amdgpu_dm/ |
D | amdgpu_dm_plane.c | 190 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
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/linux-6.12.1/drivers/gpu/drm/amd/include/ |
D | navi10_enum.h | 1549 typedef enum NUM_BANKS { enum 1555 } NUM_BANKS; typedef
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