Lines Matching refs:NUM_BANKS
87 #define NUM_BANKS(x) ((x) << 20) macro
411 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
419 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
427 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
434 NUM_BANKS(ADDR_SURF_8_BANK) | in gfx_v6_0_tiling_mode_table_init()
446 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
454 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
462 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
474 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
482 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
490 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
501 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
509 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
517 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
524 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
535 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
543 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
552 NUM_BANKS(ADDR_SURF_8_BANK); in gfx_v6_0_tiling_mode_table_init()
560 NUM_BANKS(ADDR_SURF_8_BANK); in gfx_v6_0_tiling_mode_table_init()
568 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
576 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
584 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
592 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
600 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
608 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
616 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
624 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
632 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
640 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
648 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
656 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
664 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
672 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
680 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
688 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
696 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
704 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
712 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
720 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
728 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
736 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
744 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
752 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
760 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
768 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
781 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
789 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
795 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
803 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
811 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
819 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
827 NUM_BANKS(ADDR_SURF_8_BANK) | in gfx_v6_0_tiling_mode_table_init()
841 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
849 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
857 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
864 NUM_BANKS(ADDR_SURF_8_BANK) | in gfx_v6_0_tiling_mode_table_init()
876 NUM_BANKS(ADDR_SURF_8_BANK); in gfx_v6_0_tiling_mode_table_init()
884 NUM_BANKS(ADDR_SURF_8_BANK); in gfx_v6_0_tiling_mode_table_init()
892 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
904 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
912 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
920 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
931 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
939 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
947 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
954 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
965 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
973 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
982 NUM_BANKS(ADDR_SURF_8_BANK); in gfx_v6_0_tiling_mode_table_init()
990 NUM_BANKS(ADDR_SURF_8_BANK); in gfx_v6_0_tiling_mode_table_init()
998 NUM_BANKS(ADDR_SURF_8_BANK); in gfx_v6_0_tiling_mode_table_init()
1006 NUM_BANKS(ADDR_SURF_8_BANK); in gfx_v6_0_tiling_mode_table_init()
1014 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
1022 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
1030 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
1038 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
1046 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
1054 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
1065 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
1073 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
1081 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
1088 NUM_BANKS(ADDR_SURF_4_BANK) | in gfx_v6_0_tiling_mode_table_init()
1100 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
1108 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
1116 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
1128 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
1136 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
1144 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
1155 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
1163 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
1171 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
1178 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
1189 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
1197 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
1206 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
1214 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
1222 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
1230 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
1238 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
1246 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
1254 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
1262 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
1270 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
1278 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()