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Searched refs:CV1800_CLK_BIT (Results 1 – 4 of 4) sorted by relevance

/linux-6.12.1/drivers/clk/sophgo/
Dclk-cv18xx-ip.h74 .gate = CV1800_CLK_BIT(_gate_reg, _gate_shift), \
83 .gate = CV1800_CLK_BIT(_gate_reg, \
98 .gate = CV1800_CLK_BIT(_gate_reg, \
123 .bypass = CV1800_CLK_BIT(_bypass_reg, _bypass_shift), \
143 .bypass = CV1800_CLK_BIT(_bypass_reg, _bypass_shift), \
154 .gate = CV1800_CLK_BIT(_gate_reg, \
186 .bypass = CV1800_CLK_BIT(_bypass_reg, _bypass_shift), \
203 .gate = CV1800_CLK_BIT(_gate_reg, _gate_shift),\
218 .bypass = CV1800_CLK_BIT(_bypass_reg, \
220 .clk_sel = CV1800_CLK_BIT(_clk_sel_reg, \
[all …]
Dclk-cv18xx-pll.h90 .pll_pwd = CV1800_CLK_BIT(_pll_pwd_reg, \
92 .pll_status = CV1800_CLK_BIT(_pll_status_reg, \
107 .pll_pwd = CV1800_CLK_BIT(_pll_pwd_reg, \
109 .pll_status = CV1800_CLK_BIT(_pll_status_reg, \
Dclk-cv1800.c83 .en = CV1800_CLK_BIT(REG_PLL_G6_SSC_SYN_CTRL, 2),
84 .clk_half = CV1800_CLK_BIT(REG_PLL_G6_SSC_SYN_CTRL, 0),
97 .en = CV1800_CLK_BIT(REG_PLL_G6_SSC_SYN_CTRL, 3),
98 .clk_half = CV1800_CLK_BIT(REG_PLL_G6_SSC_SYN_CTRL, 0),
111 .en = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 2),
112 .clk_half = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 0),
125 .en = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 3),
126 .clk_half = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 0),
139 .en = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 4),
140 .clk_half = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 0),
[all …]
Dclk-cv18xx-common.h45 #define CV1800_CLK_BIT(_reg, _shift) \ macro