Lines Matching refs:CV1800_CLK_BIT
83 .en = CV1800_CLK_BIT(REG_PLL_G6_SSC_SYN_CTRL, 2),
84 .clk_half = CV1800_CLK_BIT(REG_PLL_G6_SSC_SYN_CTRL, 0),
97 .en = CV1800_CLK_BIT(REG_PLL_G6_SSC_SYN_CTRL, 3),
98 .clk_half = CV1800_CLK_BIT(REG_PLL_G6_SSC_SYN_CTRL, 0),
111 .en = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 2),
112 .clk_half = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 0),
125 .en = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 3),
126 .clk_half = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 0),
139 .en = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 4),
140 .clk_half = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 0),
153 .en = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 5),
154 .clk_half = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 0),