Lines Matching refs:CV1800_CLK_BIT
74 .gate = CV1800_CLK_BIT(_gate_reg, _gate_shift), \
83 .gate = CV1800_CLK_BIT(_gate_reg, \
98 .gate = CV1800_CLK_BIT(_gate_reg, \
123 .bypass = CV1800_CLK_BIT(_bypass_reg, _bypass_shift), \
143 .bypass = CV1800_CLK_BIT(_bypass_reg, _bypass_shift), \
154 .gate = CV1800_CLK_BIT(_gate_reg, \
186 .bypass = CV1800_CLK_BIT(_bypass_reg, _bypass_shift), \
203 .gate = CV1800_CLK_BIT(_gate_reg, _gate_shift),\
218 .bypass = CV1800_CLK_BIT(_bypass_reg, \
220 .clk_sel = CV1800_CLK_BIT(_clk_sel_reg, \
238 .src_en = CV1800_CLK_BIT(_src_en_reg, \
240 .output_en = CV1800_CLK_BIT(_output_en_reg, \
242 .div_en = CV1800_CLK_BIT(_div_en_reg, \
244 .div_up = CV1800_CLK_BIT(_div_up_reg, \