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/linux-6.12.1/arch/arm64/boot/dts/xilinx/
Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
23 compatible = "xlnx,zynqmp";
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/linux-6.12.1/Documentation/devicetree/bindings/dma/xilinx/
Dxlnx,zynqmp-dpdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DisplayPort DMA Controller
10 These bindings describe the DMA engine included in the Xilinx ZynqMP
11 DisplayPort Subsystem. The DMA engine supports up to 6 DMA channels (3
12 channels for a video stream, 1 channel for a graphics stream, and 2 channels
16 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
19 - $ref: ../dma-controller.yaml#
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Dxlnx,zynqmp-dma-1.0.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DMA Engine
10 The Xilinx ZynqMP DMA engine supports memory to memory transfers,
12 control and rate control support for slave/peripheral dma access.
15 - Michael Tretter <m.tretter@pengutronix.de>
16 - Harini Katakam <harini.katakam@amd.com>
17 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
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/linux-6.12.1/drivers/dma/xilinx/
Dzynqmp_dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DMA driver for Xilinx ZynqMP DMA Engine
9 #include <linux/dma-mapping.h>
19 #include <linux/io-64-nonatomic-lo-hi.h>
25 #define ZYNQMP_DMA_ISR (chan->irq_offset + 0x100)
26 #define ZYNQMP_DMA_IMR (chan->irq_offset + 0x104)
27 #define ZYNQMP_DMA_IER (chan->irq_offset + 0x108)
28 #define ZYNQMP_DMA_IDS (chan->irq_offset + 0x10c)
68 /* Control 1 register bit field definitions */
141 #define ZYNQMP_DMA_DESC_SIZE(chan) (chan->desc_size)
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Dxilinx_dpdma.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx ZynqMP DPDMA Engine driver
5 * Copyright (C) 2015 - 2020 Xilinx, Inc.
15 #include <linux/dma/xilinx_dpdma.h>
28 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
31 #include "../virt-dma.h"
63 #define XILINX_DPDMA_EINTR_RD_AXI_ERR(n) BIT((n) + 1)
64 #define XILINX_DPDMA_EINTR_RD_AXI_ERR_MASK GENMASK(6, 1)
107 #define XILINX_DPDMA_CH_CNTL_PAUSE BIT(1)
142 * struct xilinx_dpdma_hw_desc - DPDMA hardware descriptor
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/linux-6.12.1/Documentation/devicetree/bindings/usb/
Ddwc3-xilinx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mubin Sayyed <mubin.sayyed@amd.com>
11 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
16 - enum:
17 - xlnx,zynqmp-dwc3
18 - xlnx,versal-dwc3
20 maxItems: 1
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/linux-6.12.1/Documentation/devicetree/bindings/display/xlnx/
Dxlnx,zynqmp-dpsub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DisplayPort Subsystem
10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
14 +------------------------------------------------------------+
15 +--------+ | +----------------+ +-----------+ |
16 | DPDMA | --->| | --> | Video | Video +-------------+ |
17 | 4x vid | | | | | Rendering | -+--> | | | +------+
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/linux-6.12.1/drivers/crypto/xilinx/
Dzynqmp-sha.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx ZynqMP SHA Driver.
12 #include <linux/dma-mapping.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
24 ZYNQMP_SHA3_INIT = 1,
55 tfm_ctx->dev = drv_ctx->dev; in zynqmp_sha_init_tfm()
63 tfm_ctx->fbk_tfm = fallback_tfm; in zynqmp_sha_init_tfm()
64 hash->descsize += crypto_shash_descsize(tfm_ctx->fbk_tfm); in zynqmp_sha_init_tfm()
73 if (tfm_ctx->fbk_tfm) { in zynqmp_sha_exit_tfm()
74 crypto_free_shash(tfm_ctx->fbk_tfm); in zynqmp_sha_exit_tfm()
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Dzynqmp-aes-gcm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx ZynqMP AES Driver.
12 #include <linux/dma-mapping.h>
14 #include <linux/firmware/xlnx-zynqmp.h>
25 #define ZYNQMP_KEY_SRC_SEL_KEY_LEN 1U
26 #define ZYNQMP_AES_BLK_SIZE 1U
82 struct device *dev = tfm_ctx->dev; in zynqmp_aes_aead_cipher()
92 if (tfm_ctx->keysrc == ZYNQMP_AES_KUP_KEY) in zynqmp_aes_aead_cipher()
93 dma_size = req->cryptlen + ZYNQMP_AES_KEY_SIZE in zynqmp_aes_aead_cipher()
96 dma_size = req->cryptlen + GCM_AES_IV_SIZE; in zynqmp_aes_aead_cipher()
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/linux-6.12.1/drivers/nvmem/
Dzynqmp_nvmem.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
7 #include <linux/dma-mapping.h>
9 #include <linux/nvmem-provider.h>
12 #include <linux/firmware/xlnx-zynqmp.h>
40 * struct xilinx_efuse - the basic structure
44 * @flag: 0 - represents efuse read and 1- represents efuse write
45 * @pufuserfuse:0 - represents non-puf efuses, offset is used for read/write
46 * 1 - represents puf user fuse row number.
74 return -EOPNOTSUPP; in zynqmp_efuse_access()
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/linux-6.12.1/drivers/dma/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # DMA engine configuration
7 bool "DMA Engine support"
10 DMA engines can do asynchronous data transfers without
14 DMA Device drivers supported by the configured arch, it may
18 bool "DMA Engine debugging"
22 say N here. This enables DMA engine core and driver debugging.
25 bool "DMA Engine verbose debugging"
30 the DMA engine core and drivers.
35 comment "DMA Devices"
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/linux-6.12.1/Documentation/devicetree/bindings/ata/
Dceva,ahci-1v84.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ceva,ahci-1v84.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mubin Sayyed <mubin.sayyed@amd.com>
11 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
15 special extensions to add functionality, is a high-performance dual-port
22 const: ceva,ahci-1v84
25 maxItems: 1
28 maxItems: 1
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/linux-6.12.1/drivers/spi/
Dspi-zynqmp-gqspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
6 * Copyright (C) 2009 - 2015 Xilinx, Inc.
11 #include <linux/dma-mapping.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
23 #include <linux/spi/spi-mem.h>
120 #define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
136 #define GQSPI_DEFAULT_NUM_CS 1 /* Default number of chip selects */
149 /* set to differentiate versal from zynqmp, 1=versal, 0=zynqmp */
161 * struct qspi_platform_data - zynqmp qspi platform data structure
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
66 This enables support for SPI-NAND mode on the Airoha NAND
68 is implemented as a SPI-MEM controller.
155 supports spi-mem interface.
234 this code to manage the per-word or per-transfer accesses to the
255 used by Xilinx Zynq and ZynqMP.
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Dspi-cadence-quadspi.c1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/dma-mapping.h>
16 #include <linux/firmware/xlnx-zynqmp.h>
30 #include <linux/spi/spi-mem.h>
33 #define CQSPI_NAME "cadence-qspi"
40 #define CQSPI_DISABLE_DAC_MODE BIT(1)
177 #define CQSPI_REG_READCAPTURE_DELAY_LSB 1
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/linux-6.12.1/drivers/gpu/drm/xlnx/
Dzynqmp_dpsub.c1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP DisplayPort Subsystem Driver
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 #include <linux/dma-mapping.h>
31 /* -----------------------------------------------------------------------------
39 if (!dpsub->drm) in zynqmp_dpsub_suspend()
42 return drm_mode_config_helper_suspend(&dpsub->drm->dev); in zynqmp_dpsub_suspend()
49 if (!dpsub->drm) in zynqmp_dpsub_resume()
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Dzynqmp_disp.c1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP Display Controller Driver
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
18 #include <linux/dma/xilinx_dpdma.h>
19 #include <linux/dma-mapping.h>
21 #include <linux/media-bus-format.h>
34 * --------
36 * The display controller part of ZynqMP DP subsystem, made of the Audio/Video
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Dzynqmp_kms.c1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP DisplayPort Subsystem - KMS API
5 * Copyright (C) 2017 - 2021 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
46 return container_of(drm, struct zynqmp_dpsub_drm, dev)->dpsub; in to_zynqmp_dpsub()
49 /* -----------------------------------------------------------------------------
60 if (!new_plane_state->crtc) in zynqmp_dpsub_plane_atomic_check()
63 crtc_state = drm_atomic_get_crtc_state(state, new_plane_state->crtc); in zynqmp_dpsub_plane_atomic_check()
79 struct zynqmp_dpsub *dpsub = to_zynqmp_dpsub(plane->dev); in zynqmp_dpsub_plane_atomic_disable()
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/linux-6.12.1/drivers/remoteproc/
Dxlnx_r5_remoteproc.c1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP R5 Remote Processor driver
7 #include <dt-bindings/power/xlnx-zynqmp-power.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/firmware/xlnx-zynqmp.h>
12 #include <linux/mailbox/zynqmp-ipi-message.h>
34 * reflects possible values of xlnx,cluster-mode dt-property
38 LOCKSTEP_MODE = 1, /* cores execute same code in lockstep,clk-for-clk */
43 * struct mem_bank_data - Memory Bank description
48 * @pm_domain_id: Power-domains id of memory bank for firmware to turn on/off
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/linux-6.12.1/Documentation/devicetree/bindings/pci/
Dxlnx,nwl-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
18 const: xlnx,nwl-pcie-2.11
22 - description: PCIe bridge registers location.
23 - description: PCIe Controller registers location.
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/linux-6.12.1/drivers/usb/dwc3/
Ddwc3-xilinx.c1 // SPDX-License-Identifier: GPL-2.0
3 * dwc3-xilinx.c - Xilinx DWC3 controller specific glue driver
15 #include <linux/dma-mapping.h>
22 #include <linux/firmware/xlnx-zynqmp.h>
36 #define PIPE_CLK_DESELECT 1
59 reg = readl(priv_data->regs + XLNX_USB_PHY_RST_EN); in dwc3_xlnx_mask_phy_rst()
66 writel(reg, priv_data->regs + XLNX_USB_PHY_RST_EN); in dwc3_xlnx_mask_phy_rst()
71 struct device *dev = priv_data->dev; in dwc3_xlnx_init_versal()
81 /* Assert and De-assert reset */ in dwc3_xlnx_init_versal()
90 dev_err_probe(dev, ret, "failed to De-assert Reset\n"); in dwc3_xlnx_init_versal()
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/linux-6.12.1/drivers/edac/
DKconfig16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
65 When this option is enabled, it will disable the hardware-driven
69 It should be noticed that keeping both GHES and a hardware-driven
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/linux-6.12.1/drivers/net/ethernet/cadence/
Dmacb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2004-2006 Atmel Corporation
85 #define GEM_DMACFG 0x0010 /* DMA Configuration */
114 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
115 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
116 #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
117 #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
118 #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
135 #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
136 #define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */
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Dmacb_main.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2006 Atmel Corporation
10 #include <linux/clk-provider.h>
25 #include <linux/dma-mapping.h>
40 #include <linux/firmware/xlnx-zynqmp.h>
58 * (bp)->rx_ring_size)
64 * (bp)->tx_ring_size)
67 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
78 …define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX…
80 * false amba_error in TX path from the DMA assuming there is not enough
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/linux-6.12.1/drivers/mtd/nand/raw/
Darasan-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014 - 2020 Xilinx, Inc.
17 #include <linux/dma-mapping.h>
63 #define READ_READY BIT(1)
79 #define TCCS_TIME_100NS 1
114 #define ANFC_MAX_PKT_SIZE (SZ_2K - 1)
124 * struct anfc_op - Defines how to execute an operation
126 * @addr1_reg: Memory address 1 register
150 * struct anand - Defines the NAND chip related information
153 * @rb: Ready-busy line
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