Lines Matching +full:zynqmp +full:- +full:dma +full:- +full:1
1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2004-2006 Atmel Corporation
85 #define GEM_DMACFG 0x0010 /* DMA Configuration */
114 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
115 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
116 #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
117 #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
118 #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
135 #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
136 #define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */
137 #define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */
138 #define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */
139 #define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */
153 #define GEM_TISUBN 0x01bc /* 1588 Timer Increment Sub-ns */
177 #define GEM_DCFG1 0x0280 /* Design Config 1 */
208 #define GEM_IP4DST_CMP(idx) (idx * 3 + 1)
211 /* Which screening type 2 EtherType register will be used (0 - 7) */
226 #define MACB_LB_SIZE 1
227 #define MACB_LLB_OFFSET 1 /* Loop back local */
228 #define MACB_LLB_SIZE 1
230 #define MACB_RE_SIZE 1
232 #define MACB_TE_SIZE 1
234 #define MACB_MPE_SIZE 1
236 #define MACB_CLRSTAT_SIZE 1
238 #define MACB_INCSTAT_SIZE 1
240 #define MACB_WESTAT_SIZE 1
242 #define MACB_BP_SIZE 1
244 #define MACB_TSTART_SIZE 1
246 #define MACB_THALT_SIZE 1
248 #define MACB_NCR_TPF_SIZE 1
250 #define MACB_TZQ_SIZE 1
253 #define MACB_PTPUNI_SIZE 1
255 #define MACB_OSSMODE_SIZE 1
257 #define MACB_MIIONRGMII_SIZE 1
261 #define MACB_SPD_SIZE 1
262 #define MACB_FD_OFFSET 1 /* Full duplex */
263 #define MACB_FD_SIZE 1
264 #define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */
265 #define MACB_BIT_RATE_SIZE 1
267 #define MACB_JFRAME_SIZE 1
269 #define MACB_CAF_SIZE 1
271 #define MACB_NBC_SIZE 1
273 #define MACB_NCFGR_MTI_SIZE 1
275 #define MACB_UNI_SIZE 1
277 #define MACB_BIG_SIZE 1
279 #define MACB_EAE_SIZE 1
283 #define MACB_RTY_SIZE 1
285 #define MACB_PAE_SIZE 1
287 #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
291 #define MACB_RLCE_SIZE 1
293 #define MACB_DRFCS_SIZE 1
295 #define MACB_EFRHD_SIZE 1
297 #define MACB_IRXFCS_SIZE 1
301 #define GEM_ENABLE_HS_MAC_SIZE 1
304 #define GEM_FD_OFFSET 1 /* Full duplex */
305 #define GEM_FD_SIZE 1
307 #define GEM_GBE_SIZE 1
309 #define GEM_PCSSEL_SIZE 1
311 #define GEM_PAE_SIZE 1
317 #define GEM_RXCOEN_SIZE 1
319 #define GEM_SGMIIEN_SIZE 1
324 #define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */
328 #define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */
331 #define GEM_ENDIA_DESC_SIZE 1
333 #define GEM_ENDIA_PKT_SIZE 1
337 #define GEM_TXPBMS_SIZE 1
339 #define GEM_TXCOEN_SIZE 1
340 #define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */
343 #define GEM_DDRP_SIZE 1
345 #define GEM_RXEXT_SIZE 1
347 #define GEM_TXEXT_SIZE 1
348 #define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */
349 #define GEM_ADDR64_SIZE 1
354 #define GEM_ENCUTTHRU_SIZE 1
358 #define MACB_NSR_LINK_SIZE 1
359 #define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */
360 #define MACB_MDIO_SIZE 1
362 #define MACB_IDLE_SIZE 1
366 #define MACB_UBR_SIZE 1
367 #define MACB_COL_OFFSET 1 /* Collision occurred */
368 #define MACB_COL_SIZE 1
370 #define MACB_TSR_RLE_SIZE 1
372 #define MACB_TGO_SIZE 1
374 #define MACB_BEX_SIZE 1
376 #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
378 #define MACB_COMP_SIZE 1
380 #define MACB_UND_SIZE 1
384 #define MACB_BNA_SIZE 1
385 #define MACB_REC_OFFSET 1 /* Frame received */
386 #define MACB_REC_SIZE 1
388 #define MACB_OVR_SIZE 1
392 #define MACB_MFD_SIZE 1
393 #define MACB_RCOMP_OFFSET 1 /* Receive complete */
394 #define MACB_RCOMP_SIZE 1
396 #define MACB_RXUBR_SIZE 1
398 #define MACB_TXUBR_SIZE 1
400 #define MACB_ISR_TUND_SIZE 1
402 #define MACB_ISR_RLE_SIZE 1
404 #define MACB_TXERR_SIZE 1
406 #define MACB_RM9200_TBRE_SIZE 1
408 #define MACB_TCOMP_SIZE 1
410 #define MACB_ISR_LINK_SIZE 1
412 #define MACB_ISR_ROVR_SIZE 1
414 #define MACB_HRESP_SIZE 1
416 #define MACB_PFR_SIZE 1
418 #define MACB_PTZ_SIZE 1
419 #define MACB_WOL_OFFSET 14 /* Enable wake-on-lan interrupt */
420 #define MACB_WOL_SIZE 1
422 #define MACB_DRQFR_SIZE 1
424 #define MACB_SFR_SIZE 1
426 #define MACB_DRQFT_SIZE 1
428 #define MACB_SFT_SIZE 1
430 #define MACB_PDRQFR_SIZE 1
432 #define MACB_PDRSFR_SIZE 1
434 #define MACB_PDRQFT_SIZE 1
436 #define MACB_PDRSFT_SIZE 1
438 #define MACB_SRI_SIZE 1
439 #define GEM_WOL_OFFSET 28 /* Enable wake-on-lan interrupt */
440 #define GEM_WOL_SIZE 1
461 #define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */
466 #define MACB_MII_SIZE 1
467 #define MACB_EAM_OFFSET 1
468 #define MACB_EAM_SIZE 1
470 #define MACB_TX_PAUSE_SIZE 1
472 #define MACB_TX_PAUSE_ZERO_SIZE 1
476 #define MACB_RMII_SIZE 1
478 #define GEM_RGMII_SIZE 1
479 #define MACB_CLKEN_OFFSET 1
480 #define MACB_CLKEN_SIZE 1
486 #define MACB_MAG_SIZE 1
488 #define MACB_ARP_SIZE 1
490 #define MACB_SA1_SIZE 1
492 #define MACB_WOL_MTI_SIZE 1
506 #define GEM_PCSAUTONEG_SIZE 1
510 #define GEM_IRQCOR_SIZE 1
514 #define GEM_NO_PCS_SIZE 1
518 #define GEM_RX_PKT_BUFF_SIZE 1
520 #define GEM_TX_PKT_BUFF_SIZE 1
527 #define GEM_TSU_SIZE 1
531 #define GEM_PBUF_LSO_SIZE 1
533 #define GEM_PBUF_CUTTHRU_SIZE 1
535 #define GEM_DAW64_SIZE 1
555 #define GEM_HIGH_SPEED_SIZE 1
563 #define GEM_RX_SCR_BYPASS_SIZE 1
565 #define GEM_TX_SCR_BYPASS_SIZE 1
566 #define GEM_TX_EN_OFFSET 1
567 #define GEM_TX_EN_SIZE 1
569 #define GEM_SIGNAL_OK_SIZE 1
573 #define GEM_USX_BLOCK_LOCK_SIZE 1
613 #define GEM_VLANEN_SIZE 1
617 #define GEM_ETHTEN_SIZE 1
618 #define GEM_CMPA_OFFSET 13 /* Compare A - Index to screener type 2 Compare register */
621 #define GEM_CMPAEN_SIZE 1
622 #define GEM_CMPB_OFFSET 19 /* Compare B - Index to screener type 2 Compare register */
625 #define GEM_CMPBEN_SIZE 1
626 #define GEM_CMPC_OFFSET 25 /* Compare C - Index to screener type 2 Compare register */
629 #define GEM_CMPCEN_SIZE 1
643 #define GEM_T2DISMSK_SIZE 1
651 #define MACB_QUEUE_DISABLE_SIZE 1
659 #define GEM_T2COMPOFST_ETYPE 1
671 /* Transmit DMA buffer descriptor Word 1 */
673 #define GEM_DMA_TXVALID_SIZE 1
675 /* Receive DMA buffer descriptor Word 0 */
677 #define GEM_DMA_RXVALID_SIZE 1
679 /* DMA buffer descriptor Word 2 (32 bit addressing) or Word 4 (64 bit addressing) */
680 #define GEM_DMA_SECL_OFFSET 30 /* Timestamp seconds[1:0] */
685 /* DMA buffer descriptor Word 3 (32 bit addressing) or Word 5 (64 bit addressing) */
687 /* New hardware supports 12 bit precision of timestamp in DMA buffer descriptor.
694 #define GEM_DMA_SEC_TOP (1 << GEM_DMA_SEC_WIDTH)
695 #define GEM_DMA_SEC_MASK (GEM_DMA_SEC_TOP - 1)
699 #define GEM_ADDSUB_SIZE 1
702 #define MACB_CLK_DIV16 1
708 #define GEM_CLK_DIV16 1
717 #define MACB_MAN_C22_SOF 1
718 #define MACB_MAN_C22_WRITE 1
724 #define MACB_MAN_C45_WRITE 1
757 (1 << MACB_##name##_OFFSET)
759 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \
763 & ((1 << MACB_##name##_SIZE) - 1))
765 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
770 (1 << GEM_##name##_OFFSET)
772 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \
776 & ((1 << GEM_##name##_SIZE) - 1))
778 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \
783 #define macb_readl(port, reg) (port)->macb_reg_readl((port), MACB_##reg)
784 #define macb_writel(port, reg, value) (port)->macb_reg_writel((port), MACB_##reg, (value))
785 #define gem_readl(port, reg) (port)->macb_reg_readl((port), GEM_##reg)
786 #define gem_writel(port, reg, value) (port)->macb_reg_writel((port), GEM_##reg, (value))
787 #define queue_readl(queue, reg) (queue)->bp->macb_reg_readl((queue)->bp, (queue)->reg)
788 #define queue_writel(queue, reg, value) (queue)->bp->macb_reg_writel((queue)->bp, (queue)->reg, (va…
789 #define gem_readl_n(port, reg, idx) (port)->macb_reg_readl((port), GEM_##reg + idx * 4)
790 #define gem_writel_n(port, reg, idx, value) (port)->macb_reg_writel((port), GEM_##reg + idx * 4, (v…
817 /* struct macb_dma_desc - Hardware DMA descriptor
818 * @addr: DMA address of data buffer
828 #define HW_DMA_CAP_64B (1 << 0)
829 #define HW_DMA_CAP_PTP (1 << 1)
843 /* DMA descriptor bitfields */
845 #define MACB_RX_USED_SIZE 1
846 #define MACB_RX_WRAP_OFFSET 1
847 #define MACB_RX_WRAP_SIZE 1
856 #define MACB_RX_SOF_SIZE 1
858 #define MACB_RX_EOF_SIZE 1
860 #define MACB_RX_CFI_SIZE 1
864 #define MACB_RX_PRI_TAG_SIZE 1
866 #define MACB_RX_VLAN_TAG_SIZE 1
868 #define MACB_RX_TYPEID_MATCH_SIZE 1
870 #define MACB_RX_SA4_MATCH_SIZE 1
872 #define MACB_RX_SA3_MATCH_SIZE 1
874 #define MACB_RX_SA2_MATCH_SIZE 1
876 #define MACB_RX_SA1_MATCH_SIZE 1
878 #define MACB_RX_EXT_MATCH_SIZE 1
880 #define MACB_RX_UHASH_MATCH_SIZE 1
882 #define MACB_RX_MHASH_MATCH_SIZE 1
884 #define MACB_RX_BROADCAST_SIZE 1
900 #define MACB_TX_LAST_SIZE 1
902 #define MACB_TX_NOCRC_SIZE 1
908 #define MACB_TX_TCP_SEQ_SRC_SIZE 1
910 #define MACB_TX_BUF_EXHAUSTED_SIZE 1
912 #define MACB_TX_UNDERRUN_SIZE 1
914 #define MACB_TX_ERROR_SIZE 1
916 #define MACB_TX_WRAP_SIZE 1
918 #define MACB_TX_USED_SIZE 1
925 #define GEM_RX_CSUM_IP_ONLY 1
935 /* struct macb_tx_skb - data about an skb which is being transmitted
938 * @mapping: DMA address of the skb's fragment buffer
939 * @size: size of the DMA mapped buffer
950 /* Hardware-collected statistics. Used when updating the network
1026 * returned by `ethtool -S`. Also describes which net_device_stats statistics
1037 #define GEM_NDS_RXLENERR_OFFSET 1
1165 /* MACB-PTP interface: adapt to platform needs. */
1300 /* AT91RM9200 transmit queue (1 on wire + 1 queued) */
1315 struct macb_ptp_info *ptp_info; /* macb-ptp interface */
1317 struct phy *sgmii_phy; /* for ZynqMP SGMII mode */
1347 #define TSU_SEC_MAX_VAL (((u64)1 << GEM_TSEC_SIZE) - 1)
1348 #define TSU_NSEC_MAX_VAL ((1 << GEM_TN_SIZE) - 1)
1363 if (bp->tstamp_config.tx_type == TSTAMP_DISABLED) in gem_ptp_do_txstamp()
1371 if (bp->tstamp_config.rx_filter == TSTAMP_DISABLED) in gem_ptp_do_rxstamp()
1392 return !!(bp->caps & MACB_CAPS_MACB_IS_GEM); in macb_is_gem()
1397 return IS_ENABLED(CONFIG_MACB_USE_HWSTAMP) && (bp->caps & MACB_CAPS_GEM_HAS_PTP); in gem_has_ptp()
1401 * struct macb_platform_data - platform data for MACB Ethernet used for PCI registration