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Searched +full:xbar +full:- +full:cfg (Results 1 – 9 of 9) sorted by relevance

/linux-6.12.1/drivers/media/dvb-frontends/
Dmxl5xx.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2015 Ralph Metzler <rjkm@metzlerbros.de>
10 * Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved
79 u8 xbar[3]; member
126 return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1; in i2c_write()
135 return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1; in i2c_read()
140 return i2c_read(state->base->i2c, state->base->adr, data, len); in i2cread()
145 return i2c_write(state->base->i2c, state->base->adr, data, len); in i2cwrite()
160 dev_err(state->i2cdev, "i2c read error 1\n"); in read_register_unlocked()
166 dev_err(state->i2cdev, "i2c read error 2\n"); in read_register_unlocked()
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/linux-6.12.1/drivers/dma/ti/
Dedma.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
28 #include "../virt-dma.h"
70 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
100 #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
101 #define GET_NUM_QDMACH(x) ((x & 0x70) >> 4) /* bits 4-6 */
102 #define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */
103 #define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */
104 #define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */
114 * fail. Today davinci-pcm is the only user of this driver and
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/linux-6.12.1/drivers/pci/controller/
Dpci-tegra.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
256 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
327 void __iomem *cfg; member
378 writel(value, pcie->afi + offset); in afi_writel()
383 return readl(pcie->afi + offset); in afi_readl()
389 writel(value, pcie->pads + offset); in pads_writel()
394 return readl(pcie->pads + offset); in pads_readl()
429 struct tegra_pcie *pcie = bus->sysdata; in tegra_pcie_map_bus()
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/linux-6.12.1/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra124-sor.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-sor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
19 pattern: "^sor@[0-9a-f]+$"
23 - enum:
24 - nvidia,tegra124-sor
25 - nvidia,tegra210-sor
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/linux-6.12.1/drivers/net/ethernet/netronome/nfp/nfpcore/
Dnfp6000_pcie.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* Copyright (C) 2015-2018 Netronome Systems, Inc. */
93 /* Minimal size of the PCIe cfg memory we depend on being mapped,
98 #define NFP_PCIE_P2C_FIXED_SIZE(bar) (1 << (bar)->bitsize)
99 #define NFP_PCIE_P2C_BULK_SIZE(bar) (1 << (bar)->bitsize)
100 #define NFP_PCIE_P2C_GENERAL_TARGET_OFFSET(bar, x) ((x) << ((bar)->bitsize - 2))
101 #define NFP_PCIE_P2C_GENERAL_TOKEN_OFFSET(bar, x) ((x) << ((bar)->bitsize - 4))
102 #define NFP_PCIE_P2C_GENERAL_SIZE(bar) (1 << ((bar)->bitsize - 4))
116 * struct nfp_bar - describes BAR configuration and usage
176 return NFP_PCIE_BAR_PCIE2CPP_MapType_of(bar->barcfg); in nfp_bar_maptype()
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/linux-6.12.1/drivers/net/ethernet/hisilicon/hns/
Dhns_dsaf_misc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2014-2015 Hisilicon Limited.
35 if (dsaf_dev->sub_ctrl) in dsaf_write_sub()
36 dsaf_write_syscon(dsaf_dev->sub_ctrl, reg, val); in dsaf_write_sub()
38 dsaf_write_reg(dsaf_dev->sc_base, reg, val); in dsaf_write_sub()
46 if (dsaf_dev->sub_ctrl) { in dsaf_read_sub()
47 err = dsaf_read_syscon(dsaf_dev->sub_ctrl, reg, &ret); in dsaf_read_sub()
49 dev_err(dsaf_dev->dev, "dsaf_read_syscon error %d!\n", in dsaf_read_sub()
52 ret = dsaf_read_reg(dsaf_dev->sc_base, reg); in dsaf_read_sub()
75 obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dev), in hns_dsaf_acpi_ledctrl_by_port()
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/linux-6.12.1/arch/arm64/boot/dts/nvidia/
Dtegra210-p3450-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/linux-event-codes.h>
6 #include <dt-bindings/mfd/max77620.h>
12 compatible = "nvidia,p3450-0000", "nvidia,tegra210";
22 stdout-path = "serial0:115200n8";
33 hvddio-pex-supply = <&vdd_1v8>;
34 dvddio-pex-supply = <&vdd_pex_1v05>;
35 vddio-pex-ctl-supply = <&vdd_1v8>;
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/linux-6.12.1/drivers/gpu/drm/tegra/
Dsor.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
488 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl()
490 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
498 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
499 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
506 clk_disable_unprepare(sor->clk); in tegra_sor_set_parent_clock()
508 err = clk_set_parent(sor->clk_out, parent); in tegra_sor_set_parent_clock()
512 err = clk_prepare_enable(sor->clk); in tegra_sor_set_parent_clock()
535 * Implementing ->set_parent() here isn't really required because the parent
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/linux-6.12.1/drivers/accel/habanalabs/gaudi2/
Dgaudi2.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2020-2022 HabanaLabs, Ltd.
45 * since the code already has built-in support for binning of up to MAX_FAULTY_TPCS TPCs
126 #define GAUDI2_PMMU_SPI_SEI_ENABLE_MASK GENMASK(GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE - 2, 0)
127 #define GAUDI2_HMMU_SPI_SEI_ENABLE_MASK GENMASK(GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE - 1, 0)
131 #define GAUDI2_VDEC_MSIX_ENTRIES (GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM - \
134 #define ENGINE_ID_DCORE_OFFSET (GAUDI2_DCORE1_ENGINE_ID_EDMA_0 - GAUDI2_DCORE0_ENGINE_ID_EDMA_0)
164 /* HW scrambles only bits 0-25 */
906 "cfg access error",
938 "WRONG CFG FOR COMMIT IN LIN DMA"
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