Lines Matching +full:xbar +full:- +full:cfg
1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
28 #include "../virt-dma.h"
70 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
100 #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
101 #define GET_NUM_QDMACH(x) ((x & 0x70) >> 4) /* bits 4-6 */
102 #define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */
103 #define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */
104 #define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */
114 * fail. Today davinci-pcm is the only user of this driver and
121 #define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
122 #define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
129 * reg0: channel/event 0-31
130 * reg1: channel/event 32-63
133 * bit 0-4 (0x1f) is the bit offset within the register
183 * - processed_stat: the number of SG elements we have traversed
190 * - residue: The amount of bytes we have left to transfer for this desc
192 * - residue_stat: The residue in bytes of data we have covered
196 * - sg_len: Tracks the length of the current intermediate transfer,
226 struct dma_slave_config cfg; member
287 .compatible = "ti,edma3-tpcc",
295 { .compatible = "ti,edma3-tptc", },
302 return (unsigned int)__raw_readl(ecc->base + offset); in edma_read()
307 __raw_writel(val, ecc->base + offset); in edma_write()
392 struct edma_cc *ecc = echan->ecc; in edma_set_chmap()
393 int channel = EDMA_CHAN_SLOT(echan->ch_num); in edma_set_chmap()
395 if (ecc->chmap_exist) { in edma_set_chmap()
403 struct edma_cc *ecc = echan->ecc; in edma_setup_interrupt()
404 int channel = EDMA_CHAN_SLOT(echan->ch_num); in edma_setup_interrupt()
423 if (slot >= ecc->num_slots) in edma_write_slot()
425 memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE); in edma_write_slot()
432 if (slot >= ecc->num_slots) in edma_read_slot()
433 return -EINVAL; in edma_read_slot()
434 memcpy_fromio(param, ecc->base + PARM_OFFSET(slot), PARM_SIZE); in edma_read_slot()
440 * edma_alloc_slot - allocate DMA parameter RAM
459 if (ecc->chmap_exist && slot < ecc->num_channels) in edma_alloc_slot()
464 if (ecc->chmap_exist) in edma_alloc_slot()
467 slot = ecc->num_channels; in edma_alloc_slot()
469 slot = find_next_zero_bit(ecc->slot_inuse, in edma_alloc_slot()
470 ecc->num_slots, in edma_alloc_slot()
472 if (slot == ecc->num_slots) in edma_alloc_slot()
473 return -ENOMEM; in edma_alloc_slot()
474 if (!test_and_set_bit(slot, ecc->slot_inuse)) in edma_alloc_slot()
477 } else if (slot >= ecc->num_slots) { in edma_alloc_slot()
478 return -EINVAL; in edma_alloc_slot()
479 } else if (test_and_set_bit(slot, ecc->slot_inuse)) { in edma_alloc_slot()
480 return -EBUSY; in edma_alloc_slot()
485 return EDMA_CTLR_CHAN(ecc->id, slot); in edma_alloc_slot()
491 if (slot >= ecc->num_slots) in edma_free_slot()
495 clear_bit(slot, ecc->slot_inuse); in edma_free_slot()
499 * edma_link - link one parameter RAM slot to another
509 dev_warn(ecc->dev, "Ignoring eDMA instance for linking\n"); in edma_link()
513 if (from >= ecc->num_slots || to >= ecc->num_slots) in edma_link()
521 * edma_get_position - returns the current transfer point
548 struct edma_cc *ecc = echan->ecc; in edma_start()
549 int channel = EDMA_CHAN_SLOT(echan->ch_num); in edma_start()
553 if (!echan->hw_triggered) { in edma_start()
555 dev_dbg(ecc->dev, "ESR%d %08x\n", idx, in edma_start()
560 dev_dbg(ecc->dev, "ER%d %08x\n", idx, in edma_start()
568 dev_dbg(ecc->dev, "EER%d %08x\n", idx, in edma_start()
575 struct edma_cc *ecc = echan->ecc; in edma_stop()
576 int channel = EDMA_CHAN_SLOT(echan->ch_num); in edma_stop()
588 dev_dbg(ecc->dev, "EER%d %08x\n", idx, in edma_stop()
602 int channel = EDMA_CHAN_SLOT(echan->ch_num); in edma_pause()
604 edma_shadow0_write_array(echan->ecc, SH_EECR, in edma_pause()
609 /* Re-enable EDMA hardware events on the specified channel. */
612 int channel = EDMA_CHAN_SLOT(echan->ch_num); in edma_resume()
614 edma_shadow0_write_array(echan->ecc, SH_EESR, in edma_resume()
621 struct edma_cc *ecc = echan->ecc; in edma_trigger_channel()
622 int channel = EDMA_CHAN_SLOT(echan->ch_num); in edma_trigger_channel()
628 dev_dbg(ecc->dev, "ESR%d %08x\n", idx, in edma_trigger_channel()
634 struct edma_cc *ecc = echan->ecc; in edma_clean_channel()
635 int channel = EDMA_CHAN_SLOT(echan->ch_num); in edma_clean_channel()
639 dev_dbg(ecc->dev, "EMR%d %08x\n", idx, in edma_clean_channel()
653 struct edma_cc *ecc = echan->ecc; in edma_assign_channel_eventq()
654 int channel = EDMA_CHAN_SLOT(echan->ch_num); in edma_assign_channel_eventq()
659 eventq_no = ecc->default_queue; in edma_assign_channel_eventq()
660 if (eventq_no >= ecc->num_tc) in edma_assign_channel_eventq()
671 struct edma_cc *ecc = echan->ecc; in edma_alloc_channel()
672 int channel = EDMA_CHAN_SLOT(echan->ch_num); in edma_alloc_channel()
674 if (!test_bit(echan->ch_num, ecc->channels_mask)) { in edma_alloc_channel()
675 dev_err(ecc->dev, "Channel%d is reserved, can not be used!\n", in edma_alloc_channel()
676 echan->ch_num); in edma_alloc_channel()
677 return -EINVAL; in edma_alloc_channel()
720 struct edma_cc *ecc = echan->ecc; in edma_execute()
723 struct device *dev = echan->vchan.chan.device->dev; in edma_execute()
726 if (!echan->edesc) { in edma_execute()
728 vdesc = vchan_next_desc(&echan->vchan); in edma_execute()
731 list_del(&vdesc->node); in edma_execute()
732 echan->edesc = to_edma_desc(&vdesc->tx); in edma_execute()
735 edesc = echan->edesc; in edma_execute()
738 left = edesc->pset_nr - edesc->processed; in edma_execute()
740 edesc->sg_len = 0; in edma_execute()
744 j = i + edesc->processed; in edma_execute()
745 edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param); in edma_execute()
746 edesc->sg_len += edesc->pset[j].len; in edma_execute()
759 j, echan->ch_num, echan->slot[i], in edma_execute()
760 edesc->pset[j].param.opt, in edma_execute()
761 edesc->pset[j].param.src, in edma_execute()
762 edesc->pset[j].param.dst, in edma_execute()
763 edesc->pset[j].param.a_b_cnt, in edma_execute()
764 edesc->pset[j].param.ccnt, in edma_execute()
765 edesc->pset[j].param.src_dst_bidx, in edma_execute()
766 edesc->pset[j].param.src_dst_cidx, in edma_execute()
767 edesc->pset[j].param.link_bcntrld); in edma_execute()
769 if (i != (nslots - 1)) in edma_execute()
770 edma_link(ecc, echan->slot[i], echan->slot[i + 1]); in edma_execute()
773 edesc->processed += nslots; in edma_execute()
776 * If this is either the last set in a set of SG-list transactions in edma_execute()
780 if (edesc->processed == edesc->pset_nr) { in edma_execute()
781 if (edesc->cyclic) in edma_execute()
782 edma_link(ecc, echan->slot[nslots - 1], echan->slot[1]); in edma_execute()
784 edma_link(ecc, echan->slot[nslots - 1], in edma_execute()
785 echan->ecc->dummy_slot); in edma_execute()
788 if (echan->missed) { in edma_execute()
794 dev_dbg(dev, "missed event on channel %d\n", echan->ch_num); in edma_execute()
799 echan->missed = 0; in edma_execute()
800 } else if (edesc->processed <= MAX_NR_SG) { in edma_execute()
802 echan->ch_num); in edma_execute()
806 echan->ch_num, edesc->processed); in edma_execute()
817 spin_lock_irqsave(&echan->vchan.lock, flags); in edma_terminate_all()
822 * echan->edesc is NULL and exit.) in edma_terminate_all()
824 if (echan->edesc) { in edma_terminate_all()
827 if (!echan->tc && echan->edesc->cyclic) in edma_terminate_all()
830 vchan_terminate_vdesc(&echan->edesc->vdesc); in edma_terminate_all()
831 echan->edesc = NULL; in edma_terminate_all()
834 vchan_get_all_descriptors(&echan->vchan, &head); in edma_terminate_all()
835 spin_unlock_irqrestore(&echan->vchan.lock, flags); in edma_terminate_all()
836 vchan_dma_desc_free_list(&echan->vchan, &head); in edma_terminate_all()
845 vchan_synchronize(&echan->vchan); in edma_synchronize()
849 struct dma_slave_config *cfg) in edma_slave_config() argument
853 if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || in edma_slave_config()
854 cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) in edma_slave_config()
855 return -EINVAL; in edma_slave_config()
857 if (cfg->src_maxburst > chan->device->max_burst || in edma_slave_config()
858 cfg->dst_maxburst > chan->device->max_burst) in edma_slave_config()
859 return -EINVAL; in edma_slave_config()
861 memcpy(&echan->cfg, cfg, sizeof(echan->cfg)); in edma_slave_config()
870 if (!echan->edesc) in edma_dma_pause()
871 return -EINVAL; in edma_dma_pause()
902 struct device *dev = chan->device->dev; in edma_config_pset()
903 struct edmacc_param *param = &epset->param; in edma_config_pset()
913 * A-synced transfers. This allows for large contiguous in edma_config_pset()
918 * For the A-sync case, bcnt and ccnt are the remainder in edma_config_pset()
920 * (dma_length / acnt) by (SZ_64K -1). This is so in edma_config_pset()
922 * Note: In A-sync transfer only, bcntrld is used, but it in edma_config_pset()
924 * In this case, the best way adopted is- bccnt for the in edma_config_pset()
926 * every successive frame, bcnt will be SZ_64K-1. This in edma_config_pset()
930 ccnt = dma_length / acnt / (SZ_64K - 1); in edma_config_pset()
931 bcnt = dma_length / acnt - ccnt * (SZ_64K - 1); in edma_config_pset()
933 * If bcnt is non-zero, we have a remainder and hence an in edma_config_pset()
939 bcnt = SZ_64K - 1; in edma_config_pset()
944 * use AB-synced transfers where A count is the fifo in edma_config_pset()
948 * to SZ_64K-1. This places an upper bound on the length in edma_config_pset()
954 if (ccnt > (SZ_64K - 1)) { in edma_config_pset()
956 return -EINVAL; in edma_config_pset()
961 epset->len = dma_length; in edma_config_pset()
968 epset->addr = src_addr; in edma_config_pset()
974 epset->addr = dst_addr; in edma_config_pset()
980 epset->addr = src_addr; in edma_config_pset()
983 return -EINVAL; in edma_config_pset()
986 param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num)); in edma_config_pset()
989 param->opt |= SYNCDIM; in edma_config_pset()
991 param->src = src_addr; in edma_config_pset()
992 param->dst = dst_addr; in edma_config_pset()
994 param->src_dst_bidx = (dst_bidx << 16) | src_bidx; in edma_config_pset()
995 param->src_dst_cidx = (dst_cidx << 16) | src_cidx; in edma_config_pset()
997 param->a_b_cnt = bcnt << 16 | acnt; in edma_config_pset()
998 param->ccnt = ccnt; in edma_config_pset()
1001 * A-sync case, and in this case, a requirement of reload value in edma_config_pset()
1002 * of SZ_64K-1 only is assured. 'link' is initially set to NULL in edma_config_pset()
1005 param->link_bcntrld = 0xffffffff; in edma_config_pset()
1015 struct device *dev = chan->device->dev; in edma_prep_slave_sg()
1027 src_addr = echan->cfg.src_addr; in edma_prep_slave_sg()
1028 dev_width = echan->cfg.src_addr_width; in edma_prep_slave_sg()
1029 burst = echan->cfg.src_maxburst; in edma_prep_slave_sg()
1031 dst_addr = echan->cfg.dst_addr; in edma_prep_slave_sg()
1032 dev_width = echan->cfg.dst_addr_width; in edma_prep_slave_sg()
1033 burst = echan->cfg.dst_maxburst; in edma_prep_slave_sg()
1048 edesc->pset_nr = sg_len; in edma_prep_slave_sg()
1049 edesc->residue = 0; in edma_prep_slave_sg()
1050 edesc->direction = direction; in edma_prep_slave_sg()
1051 edesc->echan = echan; in edma_prep_slave_sg()
1057 if (echan->slot[i] < 0) { in edma_prep_slave_sg()
1058 echan->slot[i] = in edma_prep_slave_sg()
1059 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY); in edma_prep_slave_sg()
1060 if (echan->slot[i] < 0) { in edma_prep_slave_sg()
1077 ret = edma_config_pset(chan, &edesc->pset[i], src_addr, in edma_prep_slave_sg()
1085 edesc->absync = ret; in edma_prep_slave_sg()
1086 edesc->residue += sg_dma_len(sg); in edma_prep_slave_sg()
1088 if (i == sg_len - 1) in edma_prep_slave_sg()
1090 edesc->pset[i].param.opt |= TCINTEN; in edma_prep_slave_sg()
1098 edesc->pset[i].param.opt |= (TCINTEN | TCCMODE); in edma_prep_slave_sg()
1100 edesc->residue_stat = edesc->residue; in edma_prep_slave_sg()
1102 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); in edma_prep_slave_sg()
1111 struct device *dev = chan->device->dev; in edma_prep_dma_memcpy()
1121 array_size = SZ_32K - 1; in edma_prep_dma_memcpy()
1124 array_size = SZ_32K - 2; in edma_prep_dma_memcpy()
1127 array_size = SZ_32K - 4; in edma_prep_dma_memcpy()
1147 * ACNT = full_length - length1, length2 = ACNT in edma_prep_dma_memcpy()
1154 /* One slot is enough for lengths multiple of (SZ_32K -1) */ in edma_prep_dma_memcpy()
1165 edesc->pset_nr = nslots; in edma_prep_dma_memcpy()
1166 edesc->residue = edesc->residue_stat = len; in edma_prep_dma_memcpy()
1167 edesc->direction = DMA_MEM_TO_MEM; in edma_prep_dma_memcpy()
1168 edesc->echan = echan; in edma_prep_dma_memcpy()
1170 ret = edma_config_pset(chan, &edesc->pset[0], src, dest, 1, in edma_prep_dma_memcpy()
1177 edesc->absync = ret; in edma_prep_dma_memcpy()
1179 edesc->pset[0].param.opt |= ITCCHEN; in edma_prep_dma_memcpy()
1183 edesc->pset[0].param.opt |= TCINTEN; in edma_prep_dma_memcpy()
1186 edesc->pset[0].param.opt |= TCCHEN; in edma_prep_dma_memcpy()
1188 if (echan->slot[1] < 0) { in edma_prep_dma_memcpy()
1189 echan->slot[1] = edma_alloc_slot(echan->ecc, in edma_prep_dma_memcpy()
1191 if (echan->slot[1] < 0) { in edma_prep_dma_memcpy()
1202 ret = edma_config_pset(chan, &edesc->pset[1], src, dest, 1, in edma_prep_dma_memcpy()
1209 edesc->pset[1].param.opt |= ITCCHEN; in edma_prep_dma_memcpy()
1212 edesc->pset[1].param.opt |= TCINTEN; in edma_prep_dma_memcpy()
1216 edesc->polled = true; in edma_prep_dma_memcpy()
1218 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); in edma_prep_dma_memcpy()
1226 struct device *dev = chan->device->dev; in edma_prep_dma_interleaved()
1234 if (is_slave_direction(xt->dir)) in edma_prep_dma_interleaved()
1237 if (xt->frame_size != 1 || xt->numf == 0) in edma_prep_dma_interleaved()
1240 if (xt->sgl[0].size > SZ_64K || xt->numf > SZ_64K) in edma_prep_dma_interleaved()
1243 src_icg = dmaengine_get_src_icg(xt, &xt->sgl[0]); in edma_prep_dma_interleaved()
1245 src_bidx = src_icg + xt->sgl[0].size; in edma_prep_dma_interleaved()
1246 } else if (xt->src_inc) { in edma_prep_dma_interleaved()
1247 src_bidx = xt->sgl[0].size; in edma_prep_dma_interleaved()
1254 dst_icg = dmaengine_get_dst_icg(xt, &xt->sgl[0]); in edma_prep_dma_interleaved()
1256 dst_bidx = dst_icg + xt->sgl[0].size; in edma_prep_dma_interleaved()
1257 } else if (xt->dst_inc) { in edma_prep_dma_interleaved()
1258 dst_bidx = xt->sgl[0].size; in edma_prep_dma_interleaved()
1272 edesc->direction = DMA_MEM_TO_MEM; in edma_prep_dma_interleaved()
1273 edesc->echan = echan; in edma_prep_dma_interleaved()
1274 edesc->pset_nr = 1; in edma_prep_dma_interleaved()
1276 param = &edesc->pset[0].param; in edma_prep_dma_interleaved()
1278 param->src = xt->src_start; in edma_prep_dma_interleaved()
1279 param->dst = xt->dst_start; in edma_prep_dma_interleaved()
1280 param->a_b_cnt = xt->numf << 16 | xt->sgl[0].size; in edma_prep_dma_interleaved()
1281 param->ccnt = 1; in edma_prep_dma_interleaved()
1282 param->src_dst_bidx = (dst_bidx << 16) | src_bidx; in edma_prep_dma_interleaved()
1283 param->src_dst_cidx = 0; in edma_prep_dma_interleaved()
1285 param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num)); in edma_prep_dma_interleaved()
1286 param->opt |= ITCCHEN; in edma_prep_dma_interleaved()
1289 param->opt |= TCINTEN; in edma_prep_dma_interleaved()
1291 edesc->polled = true; in edma_prep_dma_interleaved()
1293 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); in edma_prep_dma_interleaved()
1302 struct device *dev = chan->device->dev; in edma_prep_dma_cyclic()
1314 src_addr = echan->cfg.src_addr; in edma_prep_dma_cyclic()
1316 dev_width = echan->cfg.src_addr_width; in edma_prep_dma_cyclic()
1317 burst = echan->cfg.src_maxburst; in edma_prep_dma_cyclic()
1320 dst_addr = echan->cfg.dst_addr; in edma_prep_dma_cyclic()
1321 dev_width = echan->cfg.dst_addr_width; in edma_prep_dma_cyclic()
1322 burst = echan->cfg.dst_maxburst; in edma_prep_dma_cyclic()
1368 edesc->cyclic = 1; in edma_prep_dma_cyclic()
1369 edesc->pset_nr = nslots; in edma_prep_dma_cyclic()
1370 edesc->residue = edesc->residue_stat = buf_len; in edma_prep_dma_cyclic()
1371 edesc->direction = direction; in edma_prep_dma_cyclic()
1372 edesc->echan = echan; in edma_prep_dma_cyclic()
1375 __func__, echan->ch_num, nslots, period_len, buf_len); in edma_prep_dma_cyclic()
1379 if (echan->slot[i] < 0) { in edma_prep_dma_cyclic()
1380 echan->slot[i] = in edma_prep_dma_cyclic()
1381 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY); in edma_prep_dma_cyclic()
1382 if (echan->slot[i] < 0) { in edma_prep_dma_cyclic()
1390 if (i == nslots - 1) { in edma_prep_dma_cyclic()
1391 memcpy(&edesc->pset[i], &edesc->pset[0], in edma_prep_dma_cyclic()
1392 sizeof(edesc->pset[0])); in edma_prep_dma_cyclic()
1396 ret = edma_config_pset(chan, &edesc->pset[i], src_addr, in edma_prep_dma_cyclic()
1422 i, echan->ch_num, echan->slot[i], in edma_prep_dma_cyclic()
1423 edesc->pset[i].param.opt, in edma_prep_dma_cyclic()
1424 edesc->pset[i].param.src, in edma_prep_dma_cyclic()
1425 edesc->pset[i].param.dst, in edma_prep_dma_cyclic()
1426 edesc->pset[i].param.a_b_cnt, in edma_prep_dma_cyclic()
1427 edesc->pset[i].param.ccnt, in edma_prep_dma_cyclic()
1428 edesc->pset[i].param.src_dst_bidx, in edma_prep_dma_cyclic()
1429 edesc->pset[i].param.src_dst_cidx, in edma_prep_dma_cyclic()
1430 edesc->pset[i].param.link_bcntrld); in edma_prep_dma_cyclic()
1432 edesc->absync = ret; in edma_prep_dma_cyclic()
1438 edesc->pset[i].param.opt |= TCINTEN; in edma_prep_dma_cyclic()
1442 edesc->pset[i].param.opt |= ITCINTEN; in edma_prep_dma_cyclic()
1447 if (!echan->tc) in edma_prep_dma_cyclic()
1450 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); in edma_prep_dma_cyclic()
1455 struct device *dev = echan->vchan.chan.device->dev; in edma_completion_handler()
1458 spin_lock(&echan->vchan.lock); in edma_completion_handler()
1459 edesc = echan->edesc; in edma_completion_handler()
1461 if (edesc->cyclic) { in edma_completion_handler()
1462 vchan_cyclic_callback(&edesc->vdesc); in edma_completion_handler()
1463 spin_unlock(&echan->vchan.lock); in edma_completion_handler()
1465 } else if (edesc->processed == edesc->pset_nr) { in edma_completion_handler()
1466 edesc->residue = 0; in edma_completion_handler()
1468 vchan_cookie_complete(&edesc->vdesc); in edma_completion_handler()
1469 echan->edesc = NULL; in edma_completion_handler()
1472 echan->ch_num); in edma_completion_handler()
1475 echan->ch_num); in edma_completion_handler()
1480 edesc->residue -= edesc->sg_len; in edma_completion_handler()
1481 edesc->residue_stat = edesc->residue; in edma_completion_handler()
1482 edesc->processed_stat = edesc->processed; in edma_completion_handler()
1487 spin_unlock(&echan->vchan.lock); in edma_completion_handler()
1499 ctlr = ecc->id; in dma_irq_handler()
1503 dev_vdbg(ecc->dev, "dma_irq_handler\n"); in dma_irq_handler()
1528 edma_completion_handler(&ecc->slave_chans[channel]); in dma_irq_handler()
1538 struct edma_cc *ecc = echan->ecc; in edma_error_handler()
1539 struct device *dev = echan->vchan.chan.device->dev; in edma_error_handler()
1543 if (!echan->edesc) in edma_error_handler()
1546 spin_lock(&echan->vchan.lock); in edma_error_handler()
1548 err = edma_read_slot(ecc, echan->slot[0], &p); in edma_error_handler()
1564 echan->missed = 1; in edma_error_handler()
1576 spin_unlock(&echan->vchan.lock); in edma_error_handler()
1598 ctlr = ecc->id; in dma_ccerr_handler()
1602 dev_vdbg(ecc->dev, "dma_ccerr_handler\n"); in dma_ccerr_handler()
1608 * Ask eDMA to re-evaluate the error registers. in dma_ccerr_handler()
1610 dev_err(ecc->dev, "%s: Error interrupt without error event!\n", in dma_ccerr_handler()
1625 dev_dbg(ecc->dev, "EMR%d 0x%08x\n", j, val); in dma_ccerr_handler()
1635 edma_error_handler(&ecc->slave_chans[k]); in dma_ccerr_handler()
1641 dev_dbg(ecc->dev, "QEMR 0x%02x\n", val); in dma_ccerr_handler()
1649 dev_warn(ecc->dev, "CCERR 0x%08x\n", val); in dma_ccerr_handler()
1668 struct edma_cc *ecc = echan->ecc; in edma_alloc_chan_resources()
1669 struct device *dev = ecc->dev; in edma_alloc_chan_resources()
1673 if (echan->tc) { in edma_alloc_chan_resources()
1674 eventq_no = echan->tc->id; in edma_alloc_chan_resources()
1675 } else if (ecc->tc_list) { in edma_alloc_chan_resources()
1677 echan->tc = &ecc->tc_list[ecc->info->default_queue]; in edma_alloc_chan_resources()
1678 eventq_no = echan->tc->id; in edma_alloc_chan_resources()
1685 echan->slot[0] = edma_alloc_slot(ecc, echan->ch_num); in edma_alloc_chan_resources()
1686 if (echan->slot[0] < 0) { in edma_alloc_chan_resources()
1688 EDMA_CHAN_SLOT(echan->ch_num)); in edma_alloc_chan_resources()
1689 ret = echan->slot[0]; in edma_alloc_chan_resources()
1693 /* Set up channel -> slot mapping for the entry slot */ in edma_alloc_chan_resources()
1694 edma_set_chmap(echan, echan->slot[0]); in edma_alloc_chan_resources()
1695 echan->alloced = true; in edma_alloc_chan_resources()
1698 EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id, in edma_alloc_chan_resources()
1699 echan->hw_triggered ? "HW" : "SW"); in edma_alloc_chan_resources()
1712 struct device *dev = echan->ecc->dev; in edma_free_chan_resources()
1718 vchan_free_chan_resources(&echan->vchan); in edma_free_chan_resources()
1722 if (echan->slot[i] >= 0) { in edma_free_chan_resources()
1723 edma_free_slot(echan->ecc, echan->slot[i]); in edma_free_chan_resources()
1724 echan->slot[i] = -1; in edma_free_chan_resources()
1729 edma_set_chmap(echan, echan->ecc->dummy_slot); in edma_free_chan_resources()
1732 if (echan->alloced) { in edma_free_chan_resources()
1734 echan->alloced = false; in edma_free_chan_resources()
1737 echan->tc = NULL; in edma_free_chan_resources()
1738 echan->hw_triggered = false; in edma_free_chan_resources()
1741 EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id); in edma_free_chan_resources()
1750 spin_lock_irqsave(&echan->vchan.lock, flags); in edma_issue_pending()
1751 if (vchan_issue_pending(&echan->vchan) && !echan->edesc) in edma_issue_pending()
1753 spin_unlock_irqrestore(&echan->vchan.lock, flags); in edma_issue_pending()
1761 * RX-FIFO, as many as 55 loops have been seen.
1767 bool dst = edesc->direction == DMA_DEV_TO_MEM; in edma_residue()
1769 struct edma_chan *echan = edesc->echan; in edma_residue()
1770 struct edma_pset *pset = edesc->pset; in edma_residue()
1772 int channel = EDMA_CHAN_SLOT(echan->ch_num); in edma_residue()
1782 pos = edma_get_position(echan->ecc, echan->slot[0], dst); in edma_residue()
1792 if (is_slave_direction(edesc->direction)) in edma_residue()
1798 while (edma_shadow0_read_array(echan->ecc, event_reg, idx) & ch_bit) { in edma_residue()
1799 pos = edma_get_position(echan->ecc, echan->slot[0], dst); in edma_residue()
1803 if (!--loop_count) { in edma_residue()
1804 dev_dbg_ratelimited(echan->vchan.chan.device->dev, in edma_residue()
1816 * We never update edesc->residue in the cyclic case, so we in edma_residue()
1820 if (edesc->cyclic) { in edma_residue()
1821 done = pos - pset->addr; in edma_residue()
1822 edesc->residue_stat = edesc->residue - done; in edma_residue()
1823 return edesc->residue_stat; in edma_residue()
1836 pset += edesc->processed_stat; in edma_residue()
1838 for (i = edesc->processed_stat; i < edesc->processed; i++, pset++) { in edma_residue()
1844 if (pos >= pset->addr && pos < pset->addr + pset->len) in edma_residue()
1845 return edesc->residue_stat - (pos - pset->addr); in edma_residue()
1848 edesc->processed_stat++; in edma_residue()
1849 edesc->residue_stat -= pset->len; in edma_residue()
1851 return edesc->residue_stat; in edma_residue()
1873 spin_lock_irqsave(&echan->vchan.lock, flags); in edma_tx_status()
1874 if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) { in edma_tx_status()
1875 txstate->residue = edma_residue(echan->edesc); in edma_tx_status()
1877 struct virt_dma_desc *vdesc = vchan_find_desc(&echan->vchan, in edma_tx_status()
1881 txstate->residue = to_edma_desc(&vdesc->tx)->residue; in edma_tx_status()
1883 txstate->residue = 0; in edma_tx_status()
1890 if (ret != DMA_COMPLETE && !txstate->residue && in edma_tx_status()
1891 echan->edesc && echan->edesc->polled && in edma_tx_status()
1892 echan->edesc->vdesc.tx.cookie == cookie) { in edma_tx_status()
1894 vchan_cookie_complete(&echan->edesc->vdesc); in edma_tx_status()
1895 echan->edesc = NULL; in edma_tx_status()
1900 spin_unlock_irqrestore(&echan->vchan.lock, flags); in edma_tx_status()
1909 while (*memcpy_channels != -1) { in edma_is_memcpy_channel()
1924 struct dma_device *s_ddev = &ecc->dma_slave; in edma_dma_init()
1926 s32 *memcpy_channels = ecc->info->memcpy_channels; in edma_dma_init()
1929 dma_cap_zero(s_ddev->cap_mask); in edma_dma_init()
1930 dma_cap_set(DMA_SLAVE, s_ddev->cap_mask); in edma_dma_init()
1931 dma_cap_set(DMA_CYCLIC, s_ddev->cap_mask); in edma_dma_init()
1932 if (ecc->legacy_mode && !memcpy_channels) { in edma_dma_init()
1933 dev_warn(ecc->dev, in edma_dma_init()
1936 dma_cap_set(DMA_MEMCPY, s_ddev->cap_mask); in edma_dma_init()
1937 dma_cap_set(DMA_INTERLEAVE, s_ddev->cap_mask); in edma_dma_init()
1938 s_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy; in edma_dma_init()
1939 s_ddev->device_prep_interleaved_dma = edma_prep_dma_interleaved; in edma_dma_init()
1940 s_ddev->directions = BIT(DMA_MEM_TO_MEM); in edma_dma_init()
1943 s_ddev->device_prep_slave_sg = edma_prep_slave_sg; in edma_dma_init()
1944 s_ddev->device_prep_dma_cyclic = edma_prep_dma_cyclic; in edma_dma_init()
1945 s_ddev->device_alloc_chan_resources = edma_alloc_chan_resources; in edma_dma_init()
1946 s_ddev->device_free_chan_resources = edma_free_chan_resources; in edma_dma_init()
1947 s_ddev->device_issue_pending = edma_issue_pending; in edma_dma_init()
1948 s_ddev->device_tx_status = edma_tx_status; in edma_dma_init()
1949 s_ddev->device_config = edma_slave_config; in edma_dma_init()
1950 s_ddev->device_pause = edma_dma_pause; in edma_dma_init()
1951 s_ddev->device_resume = edma_dma_resume; in edma_dma_init()
1952 s_ddev->device_terminate_all = edma_terminate_all; in edma_dma_init()
1953 s_ddev->device_synchronize = edma_synchronize; in edma_dma_init()
1955 s_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS; in edma_dma_init()
1956 s_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS; in edma_dma_init()
1957 s_ddev->directions |= (BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV)); in edma_dma_init()
1958 s_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; in edma_dma_init()
1959 s_ddev->max_burst = SZ_32K - 1; /* CIDX: 16bit signed */ in edma_dma_init()
1961 s_ddev->dev = ecc->dev; in edma_dma_init()
1962 INIT_LIST_HEAD(&s_ddev->channels); in edma_dma_init()
1965 m_ddev = devm_kzalloc(ecc->dev, sizeof(*m_ddev), GFP_KERNEL); in edma_dma_init()
1967 dev_warn(ecc->dev, "memcpy is disabled due to OoM\n"); in edma_dma_init()
1971 ecc->dma_memcpy = m_ddev; in edma_dma_init()
1973 dma_cap_zero(m_ddev->cap_mask); in edma_dma_init()
1974 dma_cap_set(DMA_MEMCPY, m_ddev->cap_mask); in edma_dma_init()
1975 dma_cap_set(DMA_INTERLEAVE, m_ddev->cap_mask); in edma_dma_init()
1977 m_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy; in edma_dma_init()
1978 m_ddev->device_prep_interleaved_dma = edma_prep_dma_interleaved; in edma_dma_init()
1979 m_ddev->device_alloc_chan_resources = edma_alloc_chan_resources; in edma_dma_init()
1980 m_ddev->device_free_chan_resources = edma_free_chan_resources; in edma_dma_init()
1981 m_ddev->device_issue_pending = edma_issue_pending; in edma_dma_init()
1982 m_ddev->device_tx_status = edma_tx_status; in edma_dma_init()
1983 m_ddev->device_config = edma_slave_config; in edma_dma_init()
1984 m_ddev->device_pause = edma_dma_pause; in edma_dma_init()
1985 m_ddev->device_resume = edma_dma_resume; in edma_dma_init()
1986 m_ddev->device_terminate_all = edma_terminate_all; in edma_dma_init()
1987 m_ddev->device_synchronize = edma_synchronize; in edma_dma_init()
1989 m_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS; in edma_dma_init()
1990 m_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS; in edma_dma_init()
1991 m_ddev->directions = BIT(DMA_MEM_TO_MEM); in edma_dma_init()
1992 m_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; in edma_dma_init()
1994 m_ddev->dev = ecc->dev; in edma_dma_init()
1995 INIT_LIST_HEAD(&m_ddev->channels); in edma_dma_init()
1996 } else if (!ecc->legacy_mode) { in edma_dma_init()
1997 dev_info(ecc->dev, "memcpy is disabled\n"); in edma_dma_init()
2001 for (i = 0; i < ecc->num_channels; i++) { in edma_dma_init()
2002 struct edma_chan *echan = &ecc->slave_chans[i]; in edma_dma_init()
2003 echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i); in edma_dma_init()
2004 echan->ecc = ecc; in edma_dma_init()
2005 echan->vchan.desc_free = edma_desc_free; in edma_dma_init()
2008 vchan_init(&echan->vchan, m_ddev); in edma_dma_init()
2010 vchan_init(&echan->vchan, s_ddev); in edma_dma_init()
2012 INIT_LIST_HEAD(&echan->node); in edma_dma_init()
2014 echan->slot[j] = -1; in edma_dma_init()
2029 ecc->num_region = BIT(value); in edma_setup_from_hw()
2032 ecc->num_channels = BIT(value + 1); in edma_setup_from_hw()
2035 ecc->num_qchannels = value * 2; in edma_setup_from_hw()
2038 ecc->num_slots = BIT(value + 4); in edma_setup_from_hw()
2041 ecc->num_tc = value + 1; in edma_setup_from_hw()
2043 ecc->chmap_exist = (cccfg & CHMAP_EXIST) ? true : false; in edma_setup_from_hw()
2046 dev_dbg(dev, "num_region: %u\n", ecc->num_region); in edma_setup_from_hw()
2047 dev_dbg(dev, "num_channels: %u\n", ecc->num_channels); in edma_setup_from_hw()
2048 dev_dbg(dev, "num_qchannels: %u\n", ecc->num_qchannels); in edma_setup_from_hw()
2049 dev_dbg(dev, "num_slots: %u\n", ecc->num_slots); in edma_setup_from_hw()
2050 dev_dbg(dev, "num_tc: %u\n", ecc->num_tc); in edma_setup_from_hw()
2051 dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no"); in edma_setup_from_hw()
2054 if (pdata->queue_priority_mapping) in edma_setup_from_hw()
2059 * Q0 - priority 0 in edma_setup_from_hw()
2060 * Q1 - priority 1 in edma_setup_from_hw()
2061 * Q2 - priority 2 in edma_setup_from_hw()
2067 queue_priority_map = devm_kcalloc(dev, ecc->num_tc + 1, sizeof(s8), in edma_setup_from_hw()
2070 return -ENOMEM; in edma_setup_from_hw()
2072 for (i = 0; i < ecc->num_tc; i++) { in edma_setup_from_hw()
2076 queue_priority_map[i][0] = -1; in edma_setup_from_hw()
2077 queue_priority_map[i][1] = -1; in edma_setup_from_hw()
2079 pdata->queue_priority_mapping = queue_priority_map; in edma_setup_from_hw()
2081 pdata->default_queue = i - 1; in edma_setup_from_hw()
2090 const char pname[] = "ti,edma-xbar-event-map"; in edma_xbar_event_map()
2092 void __iomem *xbar; in edma_xbar_event_map() local
2100 return -ENOMEM; in edma_xbar_event_map()
2102 ret = of_address_to_resource(dev->of_node, 1, &res); in edma_xbar_event_map()
2104 return -ENOMEM; in edma_xbar_event_map()
2106 xbar = devm_ioremap(dev, res.start, resource_size(&res)); in edma_xbar_event_map()
2107 if (!xbar) in edma_xbar_event_map()
2108 return -ENOMEM; in edma_xbar_event_map()
2110 ret = of_property_read_u16_array(dev->of_node, pname, (u16 *)xbar_chans, in edma_xbar_event_map()
2113 return -EIO; in edma_xbar_event_map()
2117 xbar_chans[nelm][0] = -1; in edma_xbar_event_map()
2118 xbar_chans[nelm][1] = -1; in edma_xbar_event_map()
2123 mux = readl(xbar + offset); in edma_xbar_event_map()
2126 writel(mux, (xbar + offset)); in edma_xbar_event_map()
2129 pdata->xbar_chans = (const s16 (*)[2]) xbar_chans; in edma_xbar_event_map()
2142 return ERR_PTR(-ENOMEM); in edma_setup_info_from_dt()
2145 prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map", in edma_setup_info_from_dt()
2156 prop = of_find_property(dev->of_node, "ti,edma-memcpy-channels", &sz); in edma_setup_info_from_dt()
2158 const char pname[] = "ti,edma-memcpy-channels"; in edma_setup_info_from_dt()
2165 return ERR_PTR(-ENOMEM); in edma_setup_info_from_dt()
2167 ret = of_property_read_u32_array(dev->of_node, pname, in edma_setup_info_from_dt()
2172 memcpy_ch[nelm] = -1; in edma_setup_info_from_dt()
2173 info->memcpy_channels = memcpy_ch; in edma_setup_info_from_dt()
2176 prop = of_find_property(dev->of_node, "ti,edma-reserved-slot-ranges", in edma_setup_info_from_dt()
2179 const char pname[] = "ti,edma-reserved-slot-ranges"; in edma_setup_info_from_dt()
2191 return ERR_PTR(-ENOMEM); in edma_setup_info_from_dt()
2196 return ERR_PTR(-ENOMEM); in edma_setup_info_from_dt()
2203 return ERR_PTR(-ENOMEM); in edma_setup_info_from_dt()
2206 ret = of_property_read_u32_array(dev->of_node, pname, in edma_setup_info_from_dt()
2217 rsv_slots[nelm][0] = -1; in edma_setup_info_from_dt()
2218 rsv_slots[nelm][1] = -1; in edma_setup_info_from_dt()
2220 info->rsv = rsv_info; in edma_setup_info_from_dt()
2221 info->rsv->rsv_slots = (const s16 (*)[2])rsv_slots; in edma_setup_info_from_dt()
2232 struct edma_cc *ecc = ofdma->of_dma_data; in of_edma_xlate()
2237 if (!ecc || dma_spec->args_count < 1) in of_edma_xlate()
2240 for (i = 0; i < ecc->num_channels; i++) { in of_edma_xlate()
2241 echan = &ecc->slave_chans[i]; in of_edma_xlate()
2242 if (echan->ch_num == dma_spec->args[0]) { in of_edma_xlate()
2243 chan = &echan->vchan.chan; in of_edma_xlate()
2251 if (echan->ecc->legacy_mode && dma_spec->args_count == 1) in of_edma_xlate()
2254 if (!echan->ecc->legacy_mode && dma_spec->args_count == 2 && in of_edma_xlate()
2255 dma_spec->args[1] < echan->ecc->num_tc) { in of_edma_xlate()
2256 echan->tc = &echan->ecc->tc_list[dma_spec->args[1]]; in of_edma_xlate()
2263 echan->hw_triggered = true; in of_edma_xlate()
2270 return ERR_PTR(-EINVAL); in edma_setup_info_from_dt()
2284 struct edma_soc_info *info = pdev->dev.platform_data; in edma_probe()
2290 struct device_node *node = pdev->dev.of_node; in edma_probe()
2291 struct device *dev = &pdev->dev; in edma_probe()
2300 if (match && (*(u32 *)match->data) == EDMA_BINDING_TPCC) in edma_probe()
2311 return -ENODEV; in edma_probe()
2319 return -ENOMEM; in edma_probe()
2321 ecc->dev = dev; in edma_probe()
2322 ecc->id = pdev->id; in edma_probe()
2323 ecc->legacy_mode = legacy_mode; in edma_probe()
2324 /* When booting with DT the pdev->id is -1 */ in edma_probe()
2325 if (ecc->id < 0) in edma_probe()
2326 ecc->id = 0; in edma_probe()
2334 return -ENODEV; in edma_probe()
2337 ecc->base = devm_ioremap_resource(dev, mem); in edma_probe()
2338 if (IS_ERR(ecc->base)) in edma_probe()
2339 return PTR_ERR(ecc->base); in edma_probe()
2357 ecc->slave_chans = devm_kcalloc(dev, ecc->num_channels, in edma_probe()
2358 sizeof(*ecc->slave_chans), GFP_KERNEL); in edma_probe()
2360 ecc->slot_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots), in edma_probe()
2363 ecc->channels_mask = devm_kcalloc(dev, in edma_probe()
2364 BITS_TO_LONGS(ecc->num_channels), in edma_probe()
2366 if (!ecc->slave_chans || !ecc->slot_inuse || !ecc->channels_mask) { in edma_probe()
2367 ret = -ENOMEM; in edma_probe()
2372 bitmap_fill(ecc->channels_mask, ecc->num_channels); in edma_probe()
2374 ecc->default_queue = info->default_queue; in edma_probe()
2376 if (info->rsv) { in edma_probe()
2378 reserved = info->rsv->rsv_slots; in edma_probe()
2380 for (i = 0; reserved[i][0] != -1; i++) in edma_probe()
2381 bitmap_set(ecc->slot_inuse, reserved[i][0], in edma_probe()
2386 reserved = info->rsv->rsv_chans; in edma_probe()
2388 for (i = 0; reserved[i][0] != -1; i++) in edma_probe()
2389 bitmap_clear(ecc->channels_mask, reserved[i][0], in edma_probe()
2394 for (i = 0; i < ecc->num_slots; i++) { in edma_probe()
2395 /* Reset only unused - not reserved - paRAM slots */ in edma_probe()
2396 if (!test_bit(i, ecc->slot_inuse)) in edma_probe()
2408 ret = -ENOMEM; in edma_probe()
2415 dev_err(dev, "CCINT (%d) failed --> %d\n", irq, ret); in edma_probe()
2418 ecc->ccint = irq; in edma_probe()
2429 ret = -ENOMEM; in edma_probe()
2436 dev_err(dev, "CCERRINT (%d) failed --> %d\n", irq, ret); in edma_probe()
2439 ecc->ccerrint = irq; in edma_probe()
2442 ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY); in edma_probe()
2443 if (ecc->dummy_slot < 0) { in edma_probe()
2445 ret = ecc->dummy_slot; in edma_probe()
2449 queue_priority_mapping = info->queue_priority_mapping; in edma_probe()
2451 if (!ecc->legacy_mode) { in edma_probe()
2456 ecc->tc_list = devm_kcalloc(dev, ecc->num_tc, in edma_probe()
2457 sizeof(*ecc->tc_list), GFP_KERNEL); in edma_probe()
2458 if (!ecc->tc_list) { in edma_probe()
2459 ret = -ENOMEM; in edma_probe()
2466 if (ret || i == ecc->num_tc) in edma_probe()
2469 ecc->tc_list[i].node = tc_args.np; in edma_probe()
2470 ecc->tc_list[i].id = i; in edma_probe()
2474 info->default_queue = i; in edma_probe()
2478 /* See if we have optional dma-channel-mask array */ in edma_probe()
2479 array_max = DIV_ROUND_UP(ecc->num_channels, BITS_PER_TYPE(u32)); in edma_probe()
2481 "dma-channel-mask", in edma_probe()
2482 (u32 *)ecc->channels_mask, in edma_probe()
2485 dev_warn(dev, "dma-channel-mask is not complete.\n"); in edma_probe()
2486 else if (ret == -EOVERFLOW || ret == -ENODATA) in edma_probe()
2488 "dma-channel-mask is out of range or empty\n"); in edma_probe()
2492 for (i = 0; queue_priority_mapping[i][0] != -1; i++) in edma_probe()
2500 ecc->info = info; in edma_probe()
2505 for (i = 0; i < ecc->num_channels; i++) { in edma_probe()
2507 if (!test_bit(i, ecc->channels_mask)) in edma_probe()
2511 edma_assign_channel_eventq(&ecc->slave_chans[i], in edma_probe()
2512 info->default_queue); in edma_probe()
2514 edma_set_chmap(&ecc->slave_chans[i], ecc->dummy_slot); in edma_probe()
2517 ecc->dma_slave.filter.map = info->slave_map; in edma_probe()
2518 ecc->dma_slave.filter.mapcnt = info->slavecnt; in edma_probe()
2519 ecc->dma_slave.filter.fn = edma_filter_fn; in edma_probe()
2521 ret = dma_async_device_register(&ecc->dma_slave); in edma_probe()
2527 if (ecc->dma_memcpy) { in edma_probe()
2528 ret = dma_async_device_register(ecc->dma_memcpy); in edma_probe()
2532 dma_async_device_unregister(&ecc->dma_slave); in edma_probe()
2545 edma_free_slot(ecc, ecc->dummy_slot); in edma_probe()
2557 &dmadev->channels, vchan.chan.device_node) { in edma_cleanupp_vchan()
2558 list_del(&echan->vchan.chan.device_node); in edma_cleanupp_vchan()
2559 tasklet_kill(&echan->vchan.task); in edma_cleanupp_vchan()
2565 struct device *dev = &pdev->dev; in edma_remove()
2568 devm_free_irq(dev, ecc->ccint, ecc); in edma_remove()
2569 devm_free_irq(dev, ecc->ccerrint, ecc); in edma_remove()
2571 edma_cleanupp_vchan(&ecc->dma_slave); in edma_remove()
2573 if (dev->of_node) in edma_remove()
2574 of_dma_controller_free(dev->of_node); in edma_remove()
2575 dma_async_device_unregister(&ecc->dma_slave); in edma_remove()
2576 if (ecc->dma_memcpy) in edma_remove()
2577 dma_async_device_unregister(ecc->dma_memcpy); in edma_remove()
2578 edma_free_slot(ecc, ecc->dummy_slot); in edma_remove()
2587 struct edma_chan *echan = ecc->slave_chans; in edma_pm_suspend()
2590 for (i = 0; i < ecc->num_channels; i++) { in edma_pm_suspend()
2601 struct edma_chan *echan = ecc->slave_chans; in edma_pm_resume()
2606 edma_write_slot(ecc, ecc->dummy_slot, &dummy_paramset); in edma_pm_resume()
2608 queue_priority_mapping = ecc->info->queue_priority_mapping; in edma_pm_resume()
2611 for (i = 0; queue_priority_mapping[i][0] != -1; i++) in edma_pm_resume()
2615 for (i = 0; i < ecc->num_channels; i++) { in edma_pm_resume()
2624 /* Set up channel -> slot mapping for the entry slot */ in edma_pm_resume()
2649 pm_runtime_enable(&pdev->dev); in edma_tptc_probe()
2650 return pm_runtime_get_sync(&pdev->dev); in edma_tptc_probe()
2656 .name = "edma3-tptc",
2665 if (chan->device->dev->driver == &edma_driver.driver) { in edma_filter_fn()
2668 if (ch_req == echan->ch_num) { in edma_filter_fn()
2670 echan->hw_triggered = true; in edma_filter_fn()