Lines Matching +full:xbar +full:- +full:cfg
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2015 Ralph Metzler <rjkm@metzlerbros.de>
10 * Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved
79 u8 xbar[3]; member
126 return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1; in i2c_write()
135 return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1; in i2c_read()
140 return i2c_read(state->base->i2c, state->base->adr, data, len); in i2cread()
145 return i2c_write(state->base->i2c, state->base->adr, data, len); in i2cwrite()
160 dev_err(state->i2cdev, "i2c read error 1\n"); in read_register_unlocked()
166 dev_err(state->i2cdev, "i2c read error 2\n"); in read_register_unlocked()
178 mutex_lock(&state->base->i2c_lock); in send_command()
179 if (state->base->fwversion > 0x02010109) { in send_command()
182 dev_info(state->i2cdev, "%s busy\n", __func__); in send_command()
183 while ((DMA_INTR_PROT_WR_CMP & val) && --count) { in send_command()
184 mutex_unlock(&state->base->i2c_lock); in send_command()
186 mutex_lock(&state->base->i2c_lock); in send_command()
191 dev_info(state->i2cdev, "%s busy\n", __func__); in send_command()
192 mutex_unlock(&state->base->i2c_lock); in send_command()
193 return -EBUSY; in send_command()
197 mutex_unlock(&state->base->i2c_lock); in send_command()
209 mutex_lock(&state->base->i2c_lock); in write_register()
211 mutex_unlock(&state->base->i2c_lock); in write_register()
213 dev_err(state->i2cdev, "i2c write error\n"); in write_register()
221 u8 *buf = state->base->buf; in write_firmware_block()
223 mutex_lock(&state->base->i2c_lock); in write_firmware_block()
234 mutex_unlock(&state->base->i2c_lock); in write_firmware_block()
236 dev_err(state->i2cdev, "fw block write failed\n"); in write_firmware_block()
249 mutex_lock(&state->base->i2c_lock); in read_register()
253 dev_err(state->i2cdev, "i2c read error 1\n"); in read_register()
257 mutex_unlock(&state->base->i2c_lock); in read_register()
260 dev_err(state->i2cdev, "i2c read error 2\n"); in read_register()
267 u8 *buf = state->base->buf; in read_register_block()
269 mutex_lock(&state->base->i2c_lock); in read_register_block()
283 mutex_unlock(&state->base->i2c_lock); in read_register_block()
335 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in init()
338 p->strength.len = 1; in init()
339 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in init()
340 p->cnr.len = 1; in init()
341 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in init()
342 p->pre_bit_error.len = 1; in init()
343 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in init()
344 p->pre_bit_count.len = 1; in init()
345 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in init()
346 p->post_bit_error.len = 1; in init()
347 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in init()
348 p->post_bit_count.len = 1; in init()
349 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in init()
356 struct mxl *state = fe->demodulator_priv; in release()
358 list_del(&state->mxl); in release()
360 state->base->count--; in release()
361 if (state->base->count == 0) { in release()
362 list_del(&state->base->mxllist); in release()
363 kfree(state->base); in release()
390 state->demod, 0, 0, 0, in cfg_scrambler()
411 abort_tune_cmd.demod_id = state->demod; in cfg_demod_abort_tune()
421 /*struct mxl *state = fe->demodulator_priv;*/ in send_master_cmd()
428 struct mxl *state = fe->demodulator_priv; in set_parameters()
429 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in set_parameters()
436 if (p->frequency < 950000 || p->frequency > 2150000) in set_parameters()
437 return -EINVAL; in set_parameters()
438 if (p->symbol_rate < 1000000 || p->symbol_rate > 45000000) in set_parameters()
439 return -EINVAL; in set_parameters()
443 switch (p->delivery_system) { in set_parameters()
449 srange = p->symbol_rate / 1000000; in set_parameters()
462 cfg_scrambler(state, p->scrambling_sequence_index); in set_parameters()
465 return -EINVAL; in set_parameters()
467 demod_chan_cfg.tuner_index = state->tuner; in set_parameters()
468 demod_chan_cfg.demod_index = state->demod; in set_parameters()
469 demod_chan_cfg.frequency_in_hz = p->frequency * 1000; in set_parameters()
470 demod_chan_cfg.symbol_rate_in_hz = p->symbol_rate; in set_parameters()
475 mutex_lock(&state->base->tune_lock); in set_parameters()
477 state->base->next_tune)) in set_parameters()
478 while (time_before(jiffies, state->base->next_tune)) in set_parameters()
480 state->base->next_tune = jiffies + msecs_to_jiffies(100); in set_parameters()
481 state->tuner_in_use = state->tuner; in set_parameters()
486 mutex_unlock(&state->base->tune_lock); in set_parameters()
494 struct mxl *state = fe->demodulator_priv; in sleep()
498 if (state->tuner_in_use != 0xffffffff) { in sleep()
499 mutex_lock(&state->base->tune_lock); in sleep()
500 state->tuner_in_use = 0xffffffff; in sleep()
501 list_for_each_entry(p, &state->base->mxls, mxl) { in sleep()
502 if (p->tuner_in_use == state->tuner) in sleep()
505 if (&p->mxl == &state->base->mxls) in sleep()
506 enable_tuner(state, state->tuner, 0); in sleep()
507 mutex_unlock(&state->base->tune_lock); in sleep()
514 struct mxl *state = fe->demodulator_priv; in read_snr()
517 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in read_snr()
519 mutex_lock(&state->base->status_lock); in read_snr()
520 HYDRA_DEMOD_STATUS_LOCK(state, state->demod); in read_snr()
522 HYDRA_DMD_STATUS_OFFSET(state->demod)), in read_snr()
524 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); in read_snr()
525 mutex_unlock(&state->base->status_lock); in read_snr()
527 p->cnr.stat[0].scale = FE_SCALE_DECIBEL; in read_snr()
528 p->cnr.stat[0].svalue = (s16)reg_data * 10; in read_snr()
535 struct mxl *state = fe->demodulator_priv; in read_ber()
536 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in read_ber()
539 mutex_lock(&state->base->status_lock); in read_ber()
540 HYDRA_DEMOD_STATUS_LOCK(state, state->demod); in read_ber()
543 HYDRA_DMD_STATUS_OFFSET(state->demod)), in read_ber()
546 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); in read_ber()
548 switch (p->delivery_system) { in read_ber()
551 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; in read_ber()
552 p->pre_bit_error.stat[0].uvalue = reg[2]; in read_ber()
553 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; in read_ber()
554 p->pre_bit_count.stat[0].uvalue = reg[3]; in read_ber()
562 HYDRA_DMD_STATUS_OFFSET(state->demod)), in read_ber()
566 switch (p->delivery_system) { in read_ber()
569 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; in read_ber()
570 p->post_bit_error.stat[0].uvalue = reg[5]; in read_ber()
571 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; in read_ber()
572 p->post_bit_count.stat[0].uvalue = reg[6]; in read_ber()
575 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; in read_ber()
576 p->post_bit_error.stat[0].uvalue = reg[1]; in read_ber()
577 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; in read_ber()
578 p->post_bit_count.stat[0].uvalue = reg[2]; in read_ber()
584 mutex_unlock(&state->base->status_lock); in read_ber()
591 struct mxl *state = fe->demodulator_priv; in read_signal_strength()
592 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in read_signal_strength()
596 mutex_lock(&state->base->status_lock); in read_signal_strength()
597 HYDRA_DEMOD_STATUS_LOCK(state, state->demod); in read_signal_strength()
599 HYDRA_DMD_STATUS_OFFSET(state->demod)), in read_signal_strength()
601 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); in read_signal_strength()
602 mutex_unlock(&state->base->status_lock); in read_signal_strength()
604 p->strength.stat[0].scale = FE_SCALE_DECIBEL; in read_signal_strength()
605 p->strength.stat[0].svalue = (s16) reg_data * 10; /* fix scale */ in read_signal_strength()
612 struct mxl *state = fe->demodulator_priv; in read_status()
613 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in read_status()
616 mutex_lock(&state->base->status_lock); in read_status()
617 HYDRA_DEMOD_STATUS_LOCK(state, state->demod); in read_status()
619 HYDRA_DMD_STATUS_OFFSET(state->demod)), in read_status()
621 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); in read_status()
622 mutex_unlock(&state->base->status_lock); in read_status()
634 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in read_status()
639 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in read_status()
640 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in read_status()
641 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in read_status()
642 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in read_status()
652 struct mxl *state = fe->demodulator_priv; in tune()
660 state->tune_time = jiffies; in tune()
682 struct mxl *state = fe->demodulator_priv; in get_frontend()
686 mutex_lock(&state->base->status_lock); in get_frontend()
687 HYDRA_DEMOD_STATUS_LOCK(state, state->demod); in get_frontend()
690 HYDRA_DMD_STATUS_OFFSET(state->demod)), in get_frontend()
696 HYDRA_DMD_STATUS_OFFSET(state->demod)), in get_frontend()
699 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); in get_frontend()
700 mutex_unlock(&state->base->status_lock); in get_frontend()
702 dev_dbg(state->i2cdev, "freq=%u delsys=%u srate=%u\n", in get_frontend()
705 p->symbol_rate = reg_data[DMD_SYMBOL_RATE_ADDR]; in get_frontend()
706 p->frequency = freq; in get_frontend()
708 * p->delivery_system = in get_frontend()
710 * p->inversion = in get_frontend()
716 p->fec_inner = conv_fec(reg_data[DMD_FEC_CODE_RATE_ADDR]); in get_frontend()
717 switch (p->delivery_system) { in get_frontend()
724 p->pilot = PILOT_OFF; in get_frontend()
727 p->pilot = PILOT_ON; in get_frontend()
737 p->modulation = QPSK; in get_frontend()
740 p->modulation = PSK_8; in get_frontend()
748 p->rolloff = ROLLOFF_20; in get_frontend()
751 p->rolloff = ROLLOFF_35; in get_frontend()
754 p->rolloff = ROLLOFF_25; in get_frontend()
761 return -EINVAL; in get_frontend()
768 struct mxl *state = fe->demodulator_priv; in set_input()
770 state->tuner = input; in set_input()
777 .name = "MaxLinear MxL5xx DVB-S/S2 tuner-demodulator",
802 if (p->i2c == i2c && p->adr == adr) in match_base()
809 if (state->base->can_clkout || !enable) in cfg_dev_xtal()
849 u32 block_size = ((MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH - in write_fw_segment()
852 u8 w_msg_buffer[MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH - in write_fw_segment()
857 (total_size - data_count) : block_size; in write_fw_segment()
888 if (mbin_ptr->header.id != MBIN_FILE_HEADER_ID) { in do_firmware_download()
889 dev_err(state->i2cdev, "%s: Invalid file header ID (%c)\n", in do_firmware_download()
890 __func__, mbin_ptr->header.id); in do_firmware_download()
891 return -EINVAL; in do_firmware_download()
896 segment_ptr = (struct MBIN_SEGMENT_T *) (&mbin_ptr->data[0]); in do_firmware_download()
897 for (index = 0; index < mbin_ptr->header.num_segments; index++) { in do_firmware_download()
898 if (segment_ptr->header.id != MBIN_SEGMENT_HEADER_ID) { in do_firmware_download()
899 dev_err(state->i2cdev, "%s: Invalid segment header ID (%c)\n", in do_firmware_download()
900 __func__, segment_ptr->header.id); in do_firmware_download()
901 return -EINVAL; in do_firmware_download()
904 &(segment_ptr->header.len24[0])); in do_firmware_download()
906 &(segment_ptr->header.address[0])); in do_firmware_download()
908 if (state->base->type == MXL_HYDRA_DEVICE_568) { in do_firmware_download()
920 (u8 *) segment_ptr->data); in do_firmware_download()
925 seg_length, (u8 *) segment_ptr->data); in do_firmware_download()
930 &(segment_ptr->data[((seg_length + 3) / 4) * 4]); in do_firmware_download()
938 u32 flen = (fh->image_size24[0] << 16) | in check_fw()
939 (fh->image_size24[1] << 8) | fh->image_size24[2]; in check_fw()
943 if (fh->id != 'M' || fh->fmt_version != '1' || flen > 0x3FFF0) { in check_fw()
944 dev_info(state->i2cdev, "Invalid FW Header\n"); in check_fw()
945 return -1; in check_fw()
950 if (cs != fh->image_checksum) { in check_fw()
951 dev_info(state->i2cdev, "Invalid FW Checksum\n"); in check_fw()
952 return -1; in check_fw()
966 return -1; in firmware_download()
974 /* Reset TX FIFO's, BBAND, XBAR */ in firmware_download()
995 /* Clear Software & Host interrupt status - (Clear on read) */ in firmware_download()
1003 if (state->base->type == MXL_HYDRA_DEVICE_568) { in firmware_download()
1025 /* Initialize XPT XBAR */ in firmware_download()
1031 return -1; in firmware_download()
1033 dev_info(state->i2cdev, "Hydra FW alive. Hail!\n"); in firmware_download()
1040 dev_sku_cfg.sku_type = state->base->sku_type; in firmware_download()
1056 if ((state->base->type == MXL_HYDRA_DEVICE_541) || in cfg_ts_pad_mux()
1057 (state->base->type == MXL_HYDRA_DEVICE_541S)) in cfg_ts_pad_mux()
1060 if ((state->base->type == MXL_HYDRA_DEVICE_581) || in cfg_ts_pad_mux()
1061 (state->base->type == MXL_HYDRA_DEVICE_581S)) in cfg_ts_pad_mux()
1067 switch (state->base->type) { in cfg_ts_pad_mux()
1321 dev_info(state->i2cdev, "DIGIO = %08x\n", val); in set_drive_strength()
1322 dev_info(state->i2cdev, "set drive_strength = %u\n", ts_drive_strength); in set_drive_strength()
1363 while (--count && ((val >> tuner) & 1) != enable) { in enable_tuner()
1368 return -1; in enable_tuner()
1370 dev_dbg(state->i2cdev, "tuner %u ready = %u\n", in enable_tuner()
1440 demod_id = state->base->ts_map[demod_id]; in config_ts()
1442 if (mpeg_out_param_ptr->enable == MXL_ENABLE) { in config_ts()
1443 if (mpeg_out_param_ptr->mpeg_mode == in config_ts()
1453 (u32)(MXL_HYDRA_NCO_CLK / mpeg_out_param_ptr->max_mpeg_clk_rate); in config_ts()
1455 if (state->base->chipversion >= 2) { in config_ts()
1464 if (mpeg_out_param_ptr->mpeg_clk_type == MXL_HYDRA_MPEG_CLK_CONTINUOUS) in config_ts()
1467 if (mpeg_out_param_ptr->mpeg_mode < MXL_HYDRA_MPEG_MODE_PARALLEL) { in config_ts()
1480 mpeg_out_param_ptr->mpeg_sync_pol); in config_ts()
1486 mpeg_out_param_ptr->mpeg_valid_pol); in config_ts()
1492 mpeg_out_param_ptr->mpeg_clk_pol); in config_ts()
1498 mpeg_out_param_ptr->mpeg_sync_pulse_width); in config_ts()
1504 mpeg_out_param_ptr->mpeg_clk_phase); in config_ts()
1510 mpeg_out_param_ptr->lsb_or_msb_first); in config_ts()
1512 switch (mpeg_out_param_ptr->mpeg_error_indication) { in config_ts()
1558 if (mpeg_out_param_ptr->mpeg_mode != MXL_HYDRA_MPEG_MODE_PARALLEL) { in config_ts()
1563 mpeg_out_param_ptr->enable); in config_ts()
1583 static int load_fw(struct mxl *state, struct mxl5xx_cfg *cfg) in load_fw() argument
1588 if (cfg->fw) in load_fw()
1589 return firmware_download(state, cfg->fw, cfg->fw_len); in load_fw()
1591 if (!cfg->fw_read) in load_fw()
1592 return -1; in load_fw()
1596 return -ENOMEM; in load_fw()
1598 cfg->fw_read(cfg->fw_priv, buf, 0x40000); in load_fw()
1609 u32 type = state->base->type; in validate_sku()
1615 return -1; in validate_sku()
1617 dev_info(state->i2cdev, "padMuxBond=%08x, prcmChipId=%08x, prcmSoCId=%08x\n", in validate_sku()
1626 state->base->type = MXL_HYDRA_DEVICE_581; in validate_sku()
1645 return -1; in validate_sku()
1648 return -1; in validate_sku()
1659 dev_info(state->i2cdev, "chipID=%08x\n", val); in get_fwinfo()
1664 dev_info(state->i2cdev, "chipVer=%08x\n", val); in get_fwinfo()
1669 dev_info(state->i2cdev, "FWVer=%08x\n", val); in get_fwinfo()
1671 state->base->fwversion = val; in get_fwinfo()
1698 static int probe(struct mxl *state, struct mxl5xx_cfg *cfg) in probe() argument
1704 state->base->ts_map = ts_map1_to_1; in probe()
1706 switch (state->base->type) { in probe()
1709 state->base->can_clkout = 1; in probe()
1710 state->base->demod_num = 8; in probe()
1711 state->base->tuner_num = 1; in probe()
1712 state->base->sku_type = MXL_HYDRA_SKU_TYPE_581; in probe()
1715 state->base->can_clkout = 1; in probe()
1716 state->base->demod_num = 8; in probe()
1717 state->base->tuner_num = 3; in probe()
1718 state->base->sku_type = MXL_HYDRA_SKU_TYPE_582; in probe()
1721 state->base->can_clkout = 0; in probe()
1722 state->base->demod_num = 8; in probe()
1723 state->base->tuner_num = 4; in probe()
1724 state->base->sku_type = MXL_HYDRA_SKU_TYPE_585; in probe()
1727 state->base->can_clkout = 0; in probe()
1728 state->base->demod_num = 4; in probe()
1729 state->base->tuner_num = 4; in probe()
1730 state->base->sku_type = MXL_HYDRA_SKU_TYPE_544; in probe()
1731 state->base->ts_map = ts_map54x; in probe()
1735 state->base->can_clkout = 0; in probe()
1736 state->base->demod_num = 4; in probe()
1737 state->base->tuner_num = 1; in probe()
1738 state->base->sku_type = MXL_HYDRA_SKU_TYPE_541; in probe()
1739 state->base->ts_map = ts_map54x; in probe()
1743 state->base->can_clkout = 0; in probe()
1744 state->base->demod_num = 6; in probe()
1745 state->base->tuner_num = 1; in probe()
1746 state->base->sku_type = MXL_HYDRA_SKU_TYPE_561; in probe()
1749 state->base->can_clkout = 0; in probe()
1750 state->base->demod_num = 8; in probe()
1751 state->base->tuner_num = 1; in probe()
1752 state->base->chan_bond = 1; in probe()
1753 state->base->sku_type = MXL_HYDRA_SKU_TYPE_568; in probe()
1756 state->base->can_clkout = 1; in probe()
1757 state->base->demod_num = 4; in probe()
1758 state->base->tuner_num = 3; in probe()
1759 state->base->sku_type = MXL_HYDRA_SKU_TYPE_542; in probe()
1760 state->base->ts_map = ts_map54x; in probe()
1765 state->base->can_clkout = 0; in probe()
1766 state->base->demod_num = 8; in probe()
1767 state->base->tuner_num = 4; in probe()
1768 state->base->sku_type = MXL_HYDRA_SKU_TYPE_584; in probe()
1780 state->base->chipversion = 0; in probe()
1782 state->base->chipversion = (chipver == 2) ? 2 : 1; in probe()
1783 dev_info(state->i2cdev, "Hydra chip version %u\n", in probe()
1784 state->base->chipversion); in probe()
1786 cfg_dev_xtal(state, cfg->clk, cfg->cap, 0); in probe()
1790 status = load_fw(state, cfg); in probe()
1799 /* supports only (0-104&139)MHz */ in probe()
1800 if (cfg->ts_clk) in probe()
1801 mpeg_interface_cfg.max_mpeg_clk_rate = cfg->ts_clk; in probe()
1815 for (j = 0; j < state->base->demod_num; j++) { in probe()
1826 struct mxl5xx_cfg *cfg, u32 demod, u32 tuner, in mxl5xx_attach() argument
1836 state->demod = demod; in mxl5xx_attach()
1837 state->tuner = tuner; in mxl5xx_attach()
1838 state->tuner_in_use = 0xffffffff; in mxl5xx_attach()
1839 state->i2cdev = &i2c->dev; in mxl5xx_attach()
1841 base = match_base(i2c, cfg->adr); in mxl5xx_attach()
1843 base->count++; in mxl5xx_attach()
1844 if (base->count > base->demod_num) in mxl5xx_attach()
1846 state->base = base; in mxl5xx_attach()
1851 base->i2c = i2c; in mxl5xx_attach()
1852 base->adr = cfg->adr; in mxl5xx_attach()
1853 base->type = cfg->type; in mxl5xx_attach()
1854 base->count = 1; in mxl5xx_attach()
1855 mutex_init(&base->i2c_lock); in mxl5xx_attach()
1856 mutex_init(&base->status_lock); in mxl5xx_attach()
1857 mutex_init(&base->tune_lock); in mxl5xx_attach()
1858 INIT_LIST_HEAD(&base->mxls); in mxl5xx_attach()
1860 state->base = base; in mxl5xx_attach()
1861 if (probe(state, cfg) < 0) { in mxl5xx_attach()
1865 list_add(&base->mxllist, &mxllist); in mxl5xx_attach()
1867 state->fe.ops = mxl_ops; in mxl5xx_attach()
1868 state->xbar[0] = 4; in mxl5xx_attach()
1869 state->xbar[1] = demod; in mxl5xx_attach()
1870 state->xbar[2] = 8; in mxl5xx_attach()
1871 state->fe.demodulator_priv = state; in mxl5xx_attach()
1874 list_add(&state->mxl, &base->mxls); in mxl5xx_attach()
1875 return &state->fe; in mxl5xx_attach()
1883 MODULE_DESCRIPTION("MaxLinear MxL5xx DVB-S/S2 tuner-demodulator driver");