| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | mediatek,topckgen.yaml | 4 $id: http://devicetree.org/schemas/clock/mediatek,topckgen.yaml#
14 The Mediatek topckgen controller provides various clocks to the system.
21 - mediatek,mt6797-topckgen
22 - mediatek,mt7622-topckgen
23 - mediatek,mt8135-topckgen
24 - mediatek,mt8173-topckgen
25 - mediatek,mt8516-topckgen
27 - const: mediatek,mt7623-topckgen
28 - const: mediatek,mt2701-topckgen
32 - mediatek,mt2701-topckgen
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/sound/ |
| D | mt8186-afe-pcm.yaml | 36 mediatek,topckgen:
38 description: The phandle of the mediatek topckgen controller
103 - mediatek,topckgen
122 mediatek,topckgen = <&topckgen>;
125 <&topckgen 15>, //CLK_TOP_AUDIO
126 <&topckgen 16>, //CLK_TOP_AUD_INTBUS
127 <&topckgen 70>, //CLK_TOP_MAINPLL_D2_D4
128 <&topckgen 17>, //CLK_TOP_AUD_1
130 <&topckgen 18>, //CLK_TOP_AUD_2
132 <&topckgen 19>, //CLK_TOP_AUD_ENGEN1
[all …]
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| D | mediatek,mt8188-afe.yaml | 34 mediatek,topckgen:
36 description: The phandle of the mediatek topckgen controller
166 - mediatek,topckgen
186 mediatek,topckgen = <&topckgen>;
196 <&topckgen 186>, //CLK_TOP_APLL12_CK_DIV0
197 <&topckgen 187>, //CLK_TOP_APLL12_CK_DIV1
198 <&topckgen 188>, //CLK_TOP_APLL12_CK_DIV2
199 <&topckgen 189>, //CLK_TOP_APLL12_CK_DIV3
200 <&topckgen 191>, //CLK_TOP_APLL12_CK_DIV9
201 <&topckgen 83>, //CLK_TOP_A1SYS_HP
[all …]
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| D | mt8195-afe-pcm.yaml | 34 mediatek,topckgen:
36 description: The phandle of the mediatek topckgen controller
138 - mediatek,topckgen
157 mediatek,topckgen = <&topckgen>;
161 <&topckgen 163>, //CLK_TOP_APLL1
162 <&topckgen 166>, //CLK_TOP_APLL2
163 <&topckgen 233>, //CLK_TOP_APLL12_DIV0
164 <&topckgen 234>, //CLK_TOP_APLL12_DIV1
165 <&topckgen 235>, //CLK_TOP_APLL12_DIV2
166 <&topckgen 236>, //CLK_TOP_APLL12_DIV3
[all …]
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| D | mediatek,mt8365-afe.yaml | 97 <&topckgen CLK_TOP_AUDIO_SEL>,
98 <&topckgen CLK_TOP_AUD_I2S0_M>,
99 <&topckgen CLK_TOP_AUD_I2S1_M>,
100 <&topckgen CLK_TOP_AUD_I2S2_M>,
101 <&topckgen CLK_TOP_AUD_I2S3_M>,
102 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
103 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
104 <&topckgen CLK_TOP_AUD_1_SEL>,
105 <&topckgen CLK_TOP_AUD_2_SEL>,
106 <&topckgen CLK_TOP_APLL_I2S0_SEL>,
[all …]
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| D | mtk-afe-pcm.txt | 26 <&topckgen TOP_AUDIO_SEL>,
27 <&topckgen TOP_AUD_INTBUS_SEL>,
28 <&topckgen TOP_APLL1_DIV0>,
29 <&topckgen TOP_APLL2_DIV0>,
30 <&topckgen TOP_I2S0_M_CK_SEL>,
31 <&topckgen TOP_I2S1_M_CK_SEL>,
32 <&topckgen TOP_I2S2_M_CK_SEL>,
33 <&topckgen TOP_I2S3_M_CK_SEL>,
34 <&topckgen TOP_I2S3_B_CK_SEL>;
|
| /linux-6.12.1/Documentation/devicetree/bindings/arm/mediatek/ |
| D | mediatek,audsys.yaml | 75 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
76 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
77 <&topckgen CLK_TOP_AUD_48K_TIMING>,
78 <&topckgen CLK_TOP_AUD_44K_TIMING>,
79 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
80 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
81 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
82 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
83 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
84 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
[all …]
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| /linux-6.12.1/arch/arm64/boot/dts/mediatek/ |
| D | mt8516.dtsi | 58 <&topckgen CLK_TOP_MAINPLL_D2>;
71 <&topckgen CLK_TOP_MAINPLL_D2>;
84 <&topckgen CLK_TOP_MAINPLL_D2>;
97 <&topckgen CLK_TOP_MAINPLL_D2>;
182 topckgen: topckgen@10000000 { label
183 compatible = "mediatek,mt8516-topckgen", "syscon";
218 clocks = <&topckgen CLK_TOP_CLK26M_D2>,
219 <&topckgen CLK_TOP_APXGPT>;
251 clocks = <&topckgen CLK_TOP_PMICWRAP_26M>,
252 <&topckgen CLK_TOP_PMICWRAP_AP>;
[all …]
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| D | mt7622.dtsi | 251 clocks = <&topckgen CLK_TOP_HIF_SEL>;
260 <&topckgen CLK_TOP_AXI_SEL>;
292 topckgen: clock-controller@10210000 { label
293 compatible = "mediatek,mt7622-topckgen";
331 clocks = <&topckgen CLK_TOP_RTC>;
395 clocks = <&topckgen CLK_TOP_UART_SEL>,
406 clocks = <&topckgen CLK_TOP_UART_SEL>,
417 clocks = <&topckgen CLK_TOP_UART_SEL>,
428 clocks = <&topckgen CLK_TOP_UART_SEL>,
439 clocks = <&topckgen CLK_TOP_PWM_SEL>,
[all …]
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| D | mt7986a.dtsi | 156 topckgen: topckgen@1001b000 { label
157 compatible = "mediatek,mt7986-topckgen", "syscon";
202 clocks = <&topckgen CLK_TOP_PWM_SEL>,
242 assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
255 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
257 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
258 <&topckgen CLK_TOP_UART_SEL>;
271 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
284 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
308 clocks = <&topckgen CLK_TOP_MPLL_D2>,
[all …]
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| D | mt8192.dtsi | 453 topckgen: syscon@10000000 { label
454 compatible = "mediatek,mt8192-topckgen", "syscon";
511 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
529 clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>,
530 <&topckgen CLK_TOP_MFG_REF_SEL>;
572 clocks = <&topckgen CLK_TOP_DISP_SEL>,
586 clocks = <&topckgen CLK_TOP_IPE_SEL>,
599 clocks = <&topckgen CLK_TOP_IMG1_SEL>,
609 clocks = <&topckgen CLK_TOP_IMG2_SEL>,
619 clocks = <&topckgen CLK_TOP_MDP_SEL>,
[all …]
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| D | mt8188.dtsi | 904 topckgen: syscon@10000000 { label
905 compatible = "mediatek,mt8188-topckgen", "syscon";
961 clocks = <&topckgen CLK_APMIXED_MFGPLL>,
962 <&topckgen CLK_TOP_MFG_CORE_TMP>;
988 clocks = <&topckgen CLK_TOP_VPP>,
989 <&topckgen CLK_TOP_CAM>,
990 <&topckgen CLK_TOP_CCU>,
991 <&topckgen CLK_TOP_IMG>,
992 <&topckgen CLK_TOP_VENC>,
993 <&topckgen CLK_TOP_VDEC>,
[all …]
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| D | mt8173.dtsi | 349 topckgen: clock-controller@10000000 { label
350 compatible = "mediatek,mt8173-topckgen";
459 clocks = <&topckgen CLK_TOP_MM_SEL>;
465 clocks = <&topckgen CLK_TOP_MM_SEL>,
466 <&topckgen CLK_TOP_VENC_SEL>;
472 clocks = <&topckgen CLK_TOP_MM_SEL>;
478 clocks = <&topckgen CLK_TOP_MM_SEL>;
485 clocks = <&topckgen CLK_TOP_MM_SEL>,
486 <&topckgen CLK_TOP_VENC_LT_SEL>;
534 <&topckgen CLK_TOP_RTC_SEL>;
[all …]
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| D | mt2712e.dtsi | 90 <&topckgen CLK_TOP_F_MP0_PLL1>;
103 <&topckgen CLK_TOP_F_MP0_PLL1>;
116 <&topckgen CLK_TOP_F_BIG_PLL1>;
246 topckgen: syscon@10000000 { label
247 compatible = "mediatek,mt2712-topckgen", "syscon";
285 clocks = <&topckgen CLK_TOP_MM_SEL>,
286 <&topckgen CLK_TOP_MFG_SEL>,
287 <&topckgen CLK_TOP_VENC_SEL>,
288 <&topckgen CLK_TOP_JPGDEC_SEL>,
289 <&topckgen CLK_TOP_A1SYS_HP_SEL>,
[all …]
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| D | mt8365.dtsi | 281 topckgen: syscon@10000000 { label
282 compatible = "mediatek,mt8365-topckgen", "syscon";
318 clocks = <&topckgen CLK_TOP_MM_SEL>,
380 clocks = <&topckgen CLK_TOP_CONN_32K>,
381 <&topckgen CLK_TOP_CONN_26M>;
389 clocks = <&topckgen CLK_TOP_MFG_SEL>;
397 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
407 clocks = <&topckgen CLK_TOP_DSP_SEL>,
408 <&topckgen CLK_TOP_DSP_26M>;
604 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
[all …]
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| D | mt8186.dtsi | 848 topckgen: syscon@10000000 { label
849 compatible = "mediatek,mt8186-topckgen", "syscon";
900 clocks = <&topckgen CLK_TOP_MFG>;
927 clocks = <&topckgen CLK_TOP_SENINF>,
928 <&topckgen CLK_TOP_SENINF1>;
936 clocks = <&topckgen CLK_TOP_USB_TOP>,
952 clocks = <&topckgen CLK_TOP_AUDIODSP>,
953 <&topckgen CLK_TOP_ADSP_BUS>;
982 clocks = <&topckgen CLK_TOP_DISP>,
983 <&topckgen CLK_TOP_MDP>,
[all …]
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| D | mt8195.dtsi | 483 topckgen: syscon@10000000 { label
484 compatible = "mediatek,mt8195-topckgen", "syscon";
544 <&topckgen CLK_TOP_MFG_CORE_TMP>;
580 clocks = <&topckgen CLK_TOP_VPP>,
581 <&topckgen CLK_TOP_CAM>,
582 <&topckgen CLK_TOP_CCU>,
583 <&topckgen CLK_TOP_IMG>,
584 <&topckgen CLK_TOP_VENC>,
585 <&topckgen CLK_TOP_VDEC>,
586 <&topckgen CLK_TOP_WPE_VPP>,
[all …]
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| D | mt8167.dtsi | 20 topckgen: topckgen@10000000 { label
21 compatible = "mediatek,mt8167-topckgen", "syscon";
51 clocks = <&topckgen CLK_TOP_SMI_MM>;
59 clocks = <&topckgen CLK_TOP_SMI_MM>,
60 <&topckgen CLK_TOP_RG_VDEC>;
67 clocks = <&topckgen CLK_TOP_SMI_MM>;
74 clocks = <&topckgen CLK_TOP_RG_AXI_MFG>,
75 <&topckgen CLK_TOP_RG_SLOW_MFG>;
|
| D | mt7981b.dtsi | 66 topckgen: clock-controller@1001b000 { label
67 compatible = "mediatek,mt7981-topckgen", "syscon";
149 clocks = <&topckgen CLK_TOP_CB_M_D2>,
150 <&topckgen CLK_TOP_SPI_SEL>,
163 clocks = <&topckgen CLK_TOP_CB_M_D2>,
164 <&topckgen CLK_TOP_SPI_SEL>,
177 clocks = <&topckgen CLK_TOP_CB_M_D2>,
178 <&topckgen CLK_TOP_SPI_SEL>,
232 clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
233 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
|
| D | mt8183.dtsi | 286 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
335 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
358 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
381 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
404 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
427 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
450 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
473 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
496 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
803 topckgen: syscon@10000000 { label
[all …]
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| /linux-6.12.1/arch/arm/boot/dts/mediatek/ |
| D | mt7629.dtsi | 98 clocks = <&topckgen CLK_TOP_HIF_SEL>;
100 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
137 topckgen: syscon@10210000 { label
138 compatible = "mediatek,mt7629-topckgen", "syscon";
215 clocks = <&topckgen CLK_TOP_UART_SEL>,
226 clocks = <&topckgen CLK_TOP_UART_SEL>,
237 clocks = <&topckgen CLK_TOP_UART_SEL>,
247 clocks = <&topckgen CLK_TOP_PWM_SEL>,
251 assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
[all …]
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| D | mt2701.dtsi | 126 topckgen: syscon@10000000 { label
127 compatible = "mediatek,mt2701-topckgen", "syscon";
156 clocks = <&topckgen CLK_TOP_MM_SEL>,
157 <&topckgen CLK_TOP_MFG_SEL>,
158 <&topckgen CLK_TOP_ETHIF_SEL>;
342 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
343 <&topckgen CLK_TOP_SPI0_SEL>,
389 <&topckgen CLK_TOP_FLASH_SEL>;
402 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
403 <&topckgen CLK_TOP_SPI1_SEL>,
[all …]
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| D | mt7623.dtsi | 226 topckgen: syscon@10000000 { label
227 compatible = "mediatek,mt7623-topckgen",
228 "mediatek,mt2701-topckgen",
277 clocks = <&topckgen CLK_TOP_MM_SEL>,
278 <&topckgen CLK_TOP_MFG_SEL>,
279 <&topckgen CLK_TOP_ETHIF_SEL>;
423 clocks = <&topckgen CLK_TOP_PWM_SEL>,
487 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
488 <&topckgen CLK_TOP_SPI0_SEL>,
552 <&topckgen CLK_TOP_FLASH_SEL>;
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/media/ |
| D | mediatek,vcodec-decoder.yaml | 175 <&topckgen CLK_TOP_UNIVPLL_D2>,
176 <&topckgen CLK_TOP_CCI400_SEL>,
177 <&topckgen CLK_TOP_VDEC_SEL>,
178 <&topckgen CLK_TOP_VCODECPLL>,
180 <&topckgen CLK_TOP_VENC_LT_SEL>,
181 <&topckgen CLK_TOP_VCODECPLL_370P5>;
190 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
191 <&topckgen CLK_TOP_CCI400_SEL>,
192 <&topckgen CLK_TOP_VDEC_SEL>,
195 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/net/ |
| D | mediatek-dwmac.yaml | 168 <&topckgen CLK_TOP_ETHER_125M_SEL>,
169 <&topckgen CLK_TOP_ETHER_50M_SEL>,
170 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
171 assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
172 <&topckgen CLK_TOP_ETHER_50M_SEL>,
173 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
174 assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
175 <&topckgen CLK_TOP_APLL1_D3>,
176 <&topckgen CLK_TOP_ETHERPLL_50M>;
|