Lines Matching full:topckgen
175 <&topckgen CLK_TOP_UNIVPLL_D2>,
176 <&topckgen CLK_TOP_CCI400_SEL>,
177 <&topckgen CLK_TOP_VDEC_SEL>,
178 <&topckgen CLK_TOP_VCODECPLL>,
180 <&topckgen CLK_TOP_VENC_LT_SEL>,
181 <&topckgen CLK_TOP_VCODECPLL_370P5>;
190 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
191 <&topckgen CLK_TOP_CCI400_SEL>,
192 <&topckgen CLK_TOP_VDEC_SEL>,
195 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
196 <&topckgen CLK_TOP_UNIVPLL_D2>,
197 <&topckgen CLK_TOP_VCODECPLL>;