Lines Matching full:topckgen
75 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
76 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
77 <&topckgen CLK_TOP_AUD_48K_TIMING>,
78 <&topckgen CLK_TOP_AUD_44K_TIMING>,
79 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
80 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
81 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
82 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
83 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
84 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
85 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
86 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
87 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
88 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
89 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
90 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
144 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
145 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
146 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
147 <&topckgen CLK_TOP_AUD_MUX2_DIV>;
148 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
149 <&topckgen CLK_TOP_AUD2PLL_90M>;