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/linux-6.12.1/Documentation/networking/dsa/
Dsja1105.rst2 NXP SJA1105 switch driver
8 The NXP SJA1105 is a family of 10 SPI-managed automotive switches:
10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and
17 100base-TX PHYs
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/linux-6.12.1/Documentation/devicetree/bindings/net/
Dmicrochip,lan966x-switch.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Lan966x Ethernet switch controller
10 - Horatiu Vultur <horatiu.vultur@microchip.com>
13 The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with
14 two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
15 it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
16 2 Quad-SGMII/Quad-USGMII interfaces.
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Dxlnx,axi-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
35 axistream-connected is specified, in which case the reg
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/linux-6.12.1/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-ipq806x.c36 #define NSS_COMMON_CLK_GATE_PTP_EN(x) BIT(0x10 + x) argument
37 #define NSS_COMMON_CLK_GATE_RGMII_RX_EN(x) BIT(0x9 + (x * 2)) argument
38 #define NSS_COMMON_CLK_GATE_RGMII_TX_EN(x) BIT(0x8 + (x * 2)) argument
39 #define NSS_COMMON_CLK_GATE_GMII_RX_EN(x) BIT(0x4 + x) argument
40 #define NSS_COMMON_CLK_GATE_GMII_TX_EN(x) BIT(0x0 + x) argument
43 #define NSS_COMMON_CLK_DIV_OFFSET(x) (x * 8) argument
47 #define NSS_COMMON_CLK_SRC_CTRL_OFFSET(x) (x) argument
50 * MAC1: QSGMII=0 SGMII=0 RGMII=1
51 * MAC2 & MAC3: QSGMII=0 SGMII=1
53 #define NSS_COMMON_CLK_SRC_CTRL_RGMII(x) 1 argument
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/linux-6.12.1/arch/mips/cavium-octeon/executive/
Dcvmx-helper-sgmii.c7 * Copyright (C) 2003-2018 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 * Functions for SGMII initialization, configuration,
35 #include <asm/octeon/cvmx-config.h>
37 #include <asm/octeon/cvmx-helper.h>
38 #include <asm/octeon/cvmx-helper-board.h>
40 #include <asm/octeon/cvmx-gmxx-defs.h>
41 #include <asm/octeon/cvmx-pcsx-defs.h>
42 #include <asm/octeon/cvmx-pcsxx-defs.h>
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/linux-6.12.1/drivers/net/ethernet/qualcomm/emac/
Demac-sgmii.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
5 /* Qualcomm Technologies, Inc. EMAC SGMII Controller driver.
15 #include "emac-mac.h"
16 #include "emac-sgmii.h"
52 if (!(adpt->phy.sgmii_ops && adpt->phy.sgmii_ops->init)) in emac_sgmii_init()
55 return adpt->phy.sgmii_ops->init(adpt); in emac_sgmii_init()
60 if (!(adpt->phy.sgmii_ops && adpt->phy.sgmii_ops->open)) in emac_sgmii_open()
63 return adpt->phy.sgmii_ops->open(adpt); in emac_sgmii_open()
68 if (!(adpt->phy.sgmii_ops && adpt->phy.sgmii_ops->close)) in emac_sgmii_close()
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/linux-6.12.1/drivers/net/phy/
Ddp83867.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/nvmem-consumer.h>
19 #include <dt-bindings/net/ti-dp83867.h>
159 #define DP83867_LED_DRV_EN(x) BIT((x) * 4) argument
160 #define DP83867_LED_DRV_VAL(x) BIT((x) * 4 + 1) argument
161 #define DP83867_LED_POLARITY(x) BIT((x) * 4 + 2) argument
212 struct net_device *ndev = phydev->attached_dev; in dp83867_set_wol()
219 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | in dp83867_set_wol()
224 if (wol->wolopts & WAKE_MAGIC) { in dp83867_set_wol()
225 mac = (const u8 *)ndev->dev_addr; in dp83867_set_wol()
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Dmxl-gpy.c1 // SPDX-License-Identifier: GPL-2.0+
52 #define PHY_IMASK_WOL BIT(15) /* Wake-on-LAN */
53 #define PHY_IMASK_ANC BIT(10) /* Auto-Neg complete */
54 #define PHY_IMASK_ADSC BIT(5) /* Link auto-downspeed detect */
75 /* SGMII */
112 /* It takes 3 seconds to fully switch out of loopback mode before
113 * it can safely re-enter loopback mode. Record the time when
133 * T = -2.5761e-11*(N^4) + 9.7332e-8*(N^3) + -1.9165e-4*(N^2) +
134 * 3.0762e-1*(N^1) + -5.2156e1
136 * where [-52.156, 137.961]C and N = [0, 1023].
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Dmarvell-88x2222.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Marvell 88x2222 dual-port multi-speed ethernet transceiver.
7 * 1000Base-X or 10GBase-R on the line side.
8 * SGMII over 1000Base-X.
36 /* 1000Base-X/SGMII Control Register */
39 /* 1000BASE-X/SGMII Status Register */
42 /* 1000Base-X Auto-Negotiation Advertisement Register */
45 /* 1000Base-X PHY Specific Status Register */
110 struct mv2222_data *priv = phydev->priv; in mv2222_set_sgmii_speed()
112 switch (phydev->speed) { in mv2222_set_sgmii_speed()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
35 Adds support for a set of LED trigger events per-PHY. Link
39 logical-or of all the link speed ones.
64 Currently tested with mpc866ads and mpc8349e-mitx.
104 - ADIN1200 - Robust,Industrial, Low Power 10/100 Ethernet PHY
105 - ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit
113 - ADIN1100 - Robust,Industrial, Low Power 10BASE-T1L Ethernet PHY
127 Currently supports the Asix Electronics PHY found in the X-Surf 100
136 found in the X-Surf 100 AX88796B package.
152 Support the Broadcom BCM54140 Quad SGMII/QSGMII PHY.
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Dbcm54140.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Broadcom BCM54140 Quad SGMII/QSGMII Copper/Fiber Gigabit PHY
13 #include "bcm-phy-lib.h"
15 /* RDB per-port registers
60 #define BCM54140_RDB_MON_CTRL_SEL_RR 3 /* meassure all round-robin */
61 #define BCM54140_RDB_MON_CTRL_PWR_DOWN BIT(0) /* power-down monitor */
80 * T = 413.35 - (0.49055 * bits[9:0])
82 #define BCM54140_HWMON_TO_TEMP(v) (413350L - (v) * 491)
83 #define BCM54140_HWMON_FROM_TEMP(v) DIV_ROUND_CLOSEST_ULL(413350L - (v), 491)
119 * pin choses between 4x SGMII and QSGMII mode:
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/linux-6.12.1/drivers/net/pcs/
Dpcs-lynx.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include <linux/pcs-lynx.h>
19 #define IF_MODE_SPEED(x) (((x) << 2) & GENMASK(3, 2)) argument
36 #define lynx_to_phylink_pcs(lynx) (&(lynx)->pcs)
41 struct mii_bus *bus = pcs->bus; in lynx_pcs_get_state_usxgmii()
42 int addr = pcs->addr; in lynx_pcs_get_state_usxgmii()
49 state->link = !!(status & MDIO_STAT1_LSTATUS); in lynx_pcs_get_state_usxgmii()
50 state->an_complete = !!(status & MDIO_AN_STAT1_COMPLETE); in lynx_pcs_get_state_usxgmii()
51 if (!state->link || !state->an_complete) in lynx_pcs_get_state_usxgmii()
68 state->link = false; in lynx_pcs_get_state_2500basex()
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Dpcs-xpcs.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pcs/pcs-xpcs.h>
17 #include "pcs-xpcs.h"
169 const struct dw_xpcs_compat *compat = &desc->compat[i]; in xpcs_find_compat()
171 for (j = 0; j < compat->num_interfaces; j++) in xpcs_find_compat()
172 if (compat->interface[j] == interface) in xpcs_find_compat()
183 compat = xpcs_find_compat(xpcs->desc, interface); in xpcs_get_an_mode()
185 return -ENODEV; in xpcs_get_an_mode()
187 return compat->an_mode; in xpcs_get_an_mode()
196 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) in __xpcs_linkmode_supported()
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/linux-6.12.1/drivers/net/ethernet/ti/
Dnetcp_sgmii.c1 // SPDX-License-Identifier: GPL-2.0
7 * Sandeep Paulraj <s-paulraj@ti.com>
8 * Wingman Kwok <w-kwok2@ti.com>
22 #define SGMII23_OFFSET(x) ((x - 2) * 0x100) argument
23 #define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : (SGMII23_OFFSET(x))) argument
25 /* SGMII registers */
26 #define SGMII_SRESET_REG(x) (SGMII_OFFSET(x) + 0x004) argument
27 #define SGMII_CTL_REG(x) (SGMII_OFFSET(x) + 0x010) argument
28 #define SGMII_STATUS_REG(x) (SGMII_OFFSET(x) + 0x014) argument
29 #define SGMII_MRADV_REG(x) (SGMII_OFFSET(x) + 0x018) argument
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/linux-6.12.1/drivers/net/dsa/b53/
Db53_serdes.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Northstar Plus switch SerDes/SGMII PHY main logic
44 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
51 dev->serdes_lane = lane; in b53_serdes_set_lane()
73 struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev; in b53_serdes_config()
74 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_config()
91 struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev; in b53_serdes_an_restart()
92 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_an_restart()
105 struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev; in b53_serdes_get_state()
106 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_get_state()
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Db53_serdes.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Northstar Plus switch SerDes/SGMII PHY definitions
11 /* Non-standard page used to access SerDes PHY registers on NorthStar Plus */
22 #define B53_SERDES_MII_REG(x) (0x20 + (x) * 2) argument
23 #define B53_SERDES_DIGITAL_CONTROL(x) (0x1e + (x) * 2) argument
104 if (!dev->ops->serdes_map_lane) in b53_serdes_map_lane()
107 return dev->ops->serdes_map_lane(dev, port); in b53_serdes_map_lane()
122 return -ENODEV; in b53_serdes_init()
/linux-6.12.1/Documentation/devicetree/bindings/net/dsa/
Dmscc,ocelot.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Ocelot Switch Family
10 - Vladimir Oltean <vladimir.oltean@nxp.com>
11 - Claudiu Manoil <claudiu.manoil@nxp.com>
12 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - UNGLinuxDriver@microchip.com
16 There are multiple switches which are either part of the Ocelot-1 family, or
20 them performs packet I/O primarily through an Ethernet port of the switch
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Dmediatek,mt7530.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
14 - Daniel Golle <daniel@makrotopia.org>
17 There are three versions of MT7530, standalone, in a multi-chip module and
18 built-into a SoC.
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/linux-6.12.1/drivers/net/dsa/
Dmt7530.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN)
27 #define TRGMII_BASE(x) (0x10000 + (x)) argument
43 #define BC_FFP(x) FIELD_PREP(BC_FFP_MASK, x) argument
45 #define UNM_FFP(x) FIELD_PREP(UNM_FFP_MASK, x) argument
47 #define UNU_FFP(x) FIELD_PREP(UNU_FFP_MASK, x) argument
50 #define MT7530_CPU_PORT(x) FIELD_PREP(MT7530_CPU_PORT_MASK, x) argument
53 #define MT7530_MIRROR_PORT_GET(x) FIELD_GET(MT7530_MIRROR_PORT_MASK, x) argument
54 #define MT7530_MIRROR_PORT_SET(x) FIELD_PREP(MT7530_MIRROR_PORT_MASK, x) argument
56 #define MT7531_QRY_FFP(x) FIELD_PREP(MT7531_QRY_FFP_MASK, x) argument
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/linux-6.12.1/drivers/net/ethernet/intel/igb/
De1000_82575.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
61 * igb_write_vfta_i350 - Write value to VLAN filter table
71 struct igb_adapter *adapter = hw->back; in igb_write_vfta_i350()
74 for (i = 10; i--;) in igb_write_vfta_i350()
78 adapter->shadow_vfta[offset] = value; in igb_write_vfta_i350()
82 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
93 switch (hw->mac.type) { in igb_sgmii_uses_mdio_82575()
114 * igb_check_for_link_media_swap - Check which M88E1112 interface linked
121 struct e1000_phy_info *phy = &hw->phy; in igb_check_for_link_media_swap()
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/linux-6.12.1/Documentation/ABI/testing/
Dsysfs-class-net-phydev24 This attribute contains the 32-bit PHY Identifier as reported
41 <empty> (not available), mii, gmii, sgmii, tbi, rev-mii,
42 rmii, rgmii, rgmii-id, rgmii-rxid, rgmii-txid, rtbi, smii
43 xgmii, moca, qsgmii, trgmii, 1000base-x, 2500base-x, rxaui,
44 xaui, 10gbase-kr, unknown
60 32-bit hexadecimal number representing a bit mask of the
62 (Ethernet MAC, switch, etc.) to the PHY driver. The flags are
/linux-6.12.1/arch/arm/boot/dts/nxp/vf/
Dvf610-zii-dev-rev-b.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "vf610-zii-dev.dtsi"
11 compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610";
13 mdio-mux {
14 compatible = "mdio-mux-gpio";
15 pinctrl-0 = <&pinctrl_mdio_mux>;
16 pinctrl-names = "default";
21 mdio-parent-bus = <&mdio1>;
22 #address-cells = <1>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/marvell/
Darmada-385-clearfog-gtr-l8.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 #include "armada-385-clearfog-gtr.dtsi"
7 compatible = "solidrun,clearfog-gtr-l8", "marvell,armada385",
11 sfp1: sfp-1 {
13 pinctrl-0 = <&cf_gtr_sfp1_pins>;
14 pinctrl-names = "default";
15 i2c-bus = <&i2c0>;
16 mod-def0-gpio = <&gpio0 24 GPIO_ACTIVE_LOW>;
17 tx-disable-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
22 switch0: ethernet-switch@4 {
[all …]
Darmada-385-clearfog-gtr.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
9 SERDES mapping -
10 0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
11 1. 6141 switch (2.5Gbps capable)
12 2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
14 4. mini PCIe CON2 - PCIe2
15 5. SFP connector, or optionally SGMII Ethernet 1512 PHY
17 USB 2.0 mapping -
18 0. USB 2.0 - 0 USB pins header CON12
[all …]
/linux-6.12.1/arch/powerpc/boot/dts/
Dxcalibur1501.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
27 #address-cells = <1>;
28 #size-cells = <0>;
33 d-cache-line-size = <32>; // 32 bytes
34 i-cache-line-size = <32>; // 32 bytes
35 d-cache-size = <0x8000>; // L1, 32K
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