Lines Matching +full:switch +full:- +full:x +full:- +full:sgmii
36 #define NSS_COMMON_CLK_GATE_PTP_EN(x) BIT(0x10 + x) argument
37 #define NSS_COMMON_CLK_GATE_RGMII_RX_EN(x) BIT(0x9 + (x * 2)) argument
38 #define NSS_COMMON_CLK_GATE_RGMII_TX_EN(x) BIT(0x8 + (x * 2)) argument
39 #define NSS_COMMON_CLK_GATE_GMII_RX_EN(x) BIT(0x4 + x) argument
40 #define NSS_COMMON_CLK_GATE_GMII_TX_EN(x) BIT(0x0 + x) argument
43 #define NSS_COMMON_CLK_DIV_OFFSET(x) (x * 8) argument
47 #define NSS_COMMON_CLK_SRC_CTRL_OFFSET(x) (x) argument
50 * MAC1: QSGMII=0 SGMII=0 RGMII=1
51 * MAC2 & MAC3: QSGMII=0 SGMII=1
53 #define NSS_COMMON_CLK_SRC_CTRL_RGMII(x) 1 argument
54 #define NSS_COMMON_CLK_SRC_CTRL_SGMII(x) ((x >= 2) ? 1 : 0) argument
56 #define NSS_COMMON_GMAC_CTL(x) (0x30 + (x * 4)) argument
78 #define QSGMII_PCS_CH_SPEED_SHIFT(x) ((x) * 4) argument
83 /* Only GMAC1/2/3 support SGMII and their CTL register are not contiguous */
84 #define QSGMII_PHY_SGMII_CTL(x) ((x == 1) ? 0x134 : \ argument
85 (0x13c + (4 * (x - 2))))
92 #define QSGMII_PHY_DEEMPHASIS_LVL(x) FIELD_PREP(QSGMII_PHY_DEEMPHASIS_LVL_MASK, (x)) argument
94 #define QSGMII_PHY_PHASE_LOOP_GAIN(x) FIELD_PREP(QSGMII_PHY_PHASE_LOOP_GAIN_MASK, (x)) argument
96 #define QSGMII_PHY_RX_DC_BIAS(x) FIELD_PREP(QSGMII_PHY_RX_DC_BIAS_MASK, (x)) argument
98 #define QSGMII_PHY_RX_INPUT_EQU(x) FIELD_PREP(QSGMII_PHY_RX_INPUT_EQU_MASK, (x)) argument
100 #define QSGMII_PHY_CDR_PI_SLEW(x) FIELD_PREP(QSGMII_PHY_CDR_PI_SLEW_MASK, (x)) argument
102 #define QSGMII_PHY_TX_SLEW(x) FIELD_PREP(QSGMII_PHY_TX_SLEW_MASK, (x)) argument
104 #define QSGMII_PHY_TX_DRV_AMP(x) FIELD_PREP(QSGMII_PHY_TX_DRV_AMP_MASK, (x)) argument
117 struct device *dev = &gmac->pdev->dev; in get_clk_div_sgmii()
120 switch (speed) { in get_clk_div_sgmii()
134 dev_err(dev, "Speed %dMbps not supported in SGMII\n", speed); in get_clk_div_sgmii()
135 return -EINVAL; in get_clk_div_sgmii()
143 struct device *dev = &gmac->pdev->dev; in get_clk_div_rgmii()
146 switch (speed) { in get_clk_div_rgmii()
161 return -EINVAL; in get_clk_div_rgmii()
172 switch (gmac->phy_mode) { in ipq806x_gmac_set_speed()
178 clk_bits = NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) | in ipq806x_gmac_set_speed()
179 NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id); in ipq806x_gmac_set_speed()
184 clk_bits = NSS_COMMON_CLK_GATE_GMII_RX_EN(gmac->id) | in ipq806x_gmac_set_speed()
185 NSS_COMMON_CLK_GATE_GMII_TX_EN(gmac->id); in ipq806x_gmac_set_speed()
189 dev_err(&gmac->pdev->dev, "Unsupported PHY mode: \"%s\"\n", in ipq806x_gmac_set_speed()
190 phy_modes(gmac->phy_mode)); in ipq806x_gmac_set_speed()
191 return -EINVAL; in ipq806x_gmac_set_speed()
195 regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val); in ipq806x_gmac_set_speed()
197 regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val); in ipq806x_gmac_set_speed()
200 regmap_read(gmac->nss_common, NSS_COMMON_CLK_DIV0, &val); in ipq806x_gmac_set_speed()
202 << NSS_COMMON_CLK_DIV_OFFSET(gmac->id)); in ipq806x_gmac_set_speed()
203 val |= div << NSS_COMMON_CLK_DIV_OFFSET(gmac->id); in ipq806x_gmac_set_speed()
204 regmap_write(gmac->nss_common, NSS_COMMON_CLK_DIV0, val); in ipq806x_gmac_set_speed()
207 regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val); in ipq806x_gmac_set_speed()
209 regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val); in ipq806x_gmac_set_speed()
216 struct device *dev = &gmac->pdev->dev; in ipq806x_gmac_of_parse()
219 ret = of_get_phy_mode(dev->of_node, &gmac->phy_mode); in ipq806x_gmac_of_parse()
222 return -EINVAL; in ipq806x_gmac_of_parse()
225 if (of_property_read_u32(dev->of_node, "qcom,id", &gmac->id) < 0) { in ipq806x_gmac_of_parse()
227 return -EINVAL; in ipq806x_gmac_of_parse()
234 if (gmac->id > 3) { in ipq806x_gmac_of_parse()
236 return -EINVAL; in ipq806x_gmac_of_parse()
239 gmac->core_clk = devm_clk_get(dev, "stmmaceth"); in ipq806x_gmac_of_parse()
240 if (IS_ERR(gmac->core_clk)) { in ipq806x_gmac_of_parse()
242 return PTR_ERR(gmac->core_clk); in ipq806x_gmac_of_parse()
244 clk_set_rate(gmac->core_clk, 266000000); in ipq806x_gmac_of_parse()
247 gmac->nss_common = syscon_regmap_lookup_by_phandle(dev->of_node, in ipq806x_gmac_of_parse()
248 "qcom,nss-common"); in ipq806x_gmac_of_parse()
249 if (IS_ERR(gmac->nss_common)) { in ipq806x_gmac_of_parse()
250 dev_err(dev, "missing nss-common node\n"); in ipq806x_gmac_of_parse()
251 return PTR_ERR(gmac->nss_common); in ipq806x_gmac_of_parse()
255 gmac->qsgmii_csr = syscon_regmap_lookup_by_phandle(dev->of_node, in ipq806x_gmac_of_parse()
256 "qcom,qsgmii-csr"); in ipq806x_gmac_of_parse()
257 if (IS_ERR(gmac->qsgmii_csr)) in ipq806x_gmac_of_parse()
258 dev_err(dev, "missing qsgmii-csr node\n"); in ipq806x_gmac_of_parse()
260 return PTR_ERR_OR_ZERO(gmac->qsgmii_csr); in ipq806x_gmac_of_parse()
273 struct platform_device *pdev = gmac->pdev; in ipq806x_gmac_configure_qsgmii_pcs_speed()
274 struct device *dev = &pdev->dev; in ipq806x_gmac_configure_qsgmii_pcs_speed()
284 if (!of_phy_is_fixed_link(pdev->dev.of_node)) in ipq806x_gmac_configure_qsgmii_pcs_speed()
287 dn = of_get_child_by_name(pdev->dev.of_node, "fixed-link"); in ipq806x_gmac_configure_qsgmii_pcs_speed()
291 dev_err(dev, "found fixed-link node with no speed"); in ipq806x_gmac_configure_qsgmii_pcs_speed()
297 switch (link_speed) { in ipq806x_gmac_configure_qsgmii_pcs_speed()
310 regmap_update_bits(gmac->qsgmii_csr, QSGMII_PCS_ALL_CH_CTL, in ipq806x_gmac_configure_qsgmii_pcs_speed()
312 QSGMII_PCS_CH_SPEED_SHIFT(gmac->id), in ipq806x_gmac_configure_qsgmii_pcs_speed()
314 QSGMII_PCS_CH_SPEED_SHIFT(gmac->id)); in ipq806x_gmac_configure_qsgmii_pcs_speed()
331 struct platform_device *pdev = gmac->pdev; in ipq806x_gmac_configure_qsgmii_params()
333 struct device *dev = &pdev->dev; in ipq806x_gmac_configure_qsgmii_params()
336 switch (gmac->id) { in ipq806x_gmac_configure_qsgmii_params()
356 default: /* gmac 0 can't be set in SGMII mode */ in ipq806x_gmac_configure_qsgmii_params()
357 dev_err(dev, "gmac id %d can't be in SGMII mode", gmac->id); in ipq806x_gmac_configure_qsgmii_params()
358 return -EINVAL; in ipq806x_gmac_configure_qsgmii_params()
371 regmap_write(gmac->qsgmii_csr, QSGMII_PHY_SGMII_CTL(gmac->id), in ipq806x_gmac_configure_qsgmii_params()
381 struct device *dev = &pdev->dev; in ipq806x_gmac_probe()
396 return -ENOMEM; in ipq806x_gmac_probe()
398 gmac->pdev = pdev; in ipq806x_gmac_probe()
406 regmap_write(gmac->qsgmii_csr, QSGMII_PCS_CAL_LCKDT_CTL, in ipq806x_gmac_probe()
414 switch (gmac->phy_mode) { in ipq806x_gmac_probe()
427 regmap_write(gmac->nss_common, NSS_COMMON_GMAC_CTL(gmac->id), val); in ipq806x_gmac_probe()
430 regmap_read(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, &val); in ipq806x_gmac_probe()
431 val &= ~(1 << NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id)); in ipq806x_gmac_probe()
432 switch (gmac->phy_mode) { in ipq806x_gmac_probe()
437 val |= NSS_COMMON_CLK_SRC_CTRL_RGMII(gmac->id) << in ipq806x_gmac_probe()
438 NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id); in ipq806x_gmac_probe()
441 val |= NSS_COMMON_CLK_SRC_CTRL_SGMII(gmac->id) << in ipq806x_gmac_probe()
442 NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id); in ipq806x_gmac_probe()
447 regmap_write(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, val); in ipq806x_gmac_probe()
450 regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val); in ipq806x_gmac_probe()
451 val |= NSS_COMMON_CLK_GATE_PTP_EN(gmac->id); in ipq806x_gmac_probe()
452 switch (gmac->phy_mode) { in ipq806x_gmac_probe()
457 val |= NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) | in ipq806x_gmac_probe()
458 NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id); in ipq806x_gmac_probe()
461 val |= NSS_COMMON_CLK_GATE_GMII_RX_EN(gmac->id) | in ipq806x_gmac_probe()
462 NSS_COMMON_CLK_GATE_GMII_TX_EN(gmac->id); in ipq806x_gmac_probe()
467 regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val); in ipq806x_gmac_probe()
469 if (gmac->phy_mode == PHY_INTERFACE_MODE_SGMII) { in ipq806x_gmac_probe()
479 plat_dat->has_gmac = true; in ipq806x_gmac_probe()
480 plat_dat->bsp_priv = gmac; in ipq806x_gmac_probe()
481 plat_dat->fix_mac_speed = ipq806x_gmac_fix_mac_speed; in ipq806x_gmac_probe()
482 plat_dat->multicast_filter_bins = 0; in ipq806x_gmac_probe()
483 plat_dat->tx_fifo_size = 8192; in ipq806x_gmac_probe()
484 plat_dat->rx_fifo_size = 8192; in ipq806x_gmac_probe()
486 return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); in ipq806x_gmac_probe()
489 dev_err(&pdev->dev, "Unsupported PHY mode: \"%s\"\n", in ipq806x_gmac_probe()
490 phy_modes(gmac->phy_mode)); in ipq806x_gmac_probe()
491 return -EINVAL; in ipq806x_gmac_probe()
495 { .compatible = "qcom,ipq806x-gmac" },
504 .name = "ipq806x-gmac-dwmac",