Lines Matching +full:switch +full:- +full:x +full:- +full:sgmii
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
61 * igb_write_vfta_i350 - Write value to VLAN filter table
71 struct igb_adapter *adapter = hw->back; in igb_write_vfta_i350()
74 for (i = 10; i--;) in igb_write_vfta_i350()
78 adapter->shadow_vfta[offset] = value; in igb_write_vfta_i350()
82 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
93 switch (hw->mac.type) { in igb_sgmii_uses_mdio_82575()
114 * igb_check_for_link_media_swap - Check which M88E1112 interface linked
121 struct e1000_phy_info *phy = &hw->phy; in igb_check_for_link_media_swap()
127 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); in igb_check_for_link_media_swap()
131 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); in igb_check_for_link_media_swap()
139 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1); in igb_check_for_link_media_swap()
143 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); in igb_check_for_link_media_swap()
152 if (port && (hw->dev_spec._82575.media_port != port)) { in igb_check_for_link_media_swap()
153 hw->dev_spec._82575.media_port = port; in igb_check_for_link_media_swap()
154 hw->dev_spec._82575.media_changed = true; in igb_check_for_link_media_swap()
159 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); in igb_check_for_link_media_swap()
166 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); in igb_check_for_link_media_swap()
175 * igb_init_phy_params_82575 - Init PHY func ptrs.
180 struct e1000_phy_info *phy = &hw->phy; in igb_init_phy_params_82575()
184 if (hw->phy.media_type != e1000_media_type_copper) { in igb_init_phy_params_82575()
185 phy->type = e1000_phy_none; in igb_init_phy_params_82575()
189 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in igb_init_phy_params_82575()
190 phy->reset_delay_us = 100; in igb_init_phy_params_82575()
195 phy->ops.reset = igb_phy_hw_reset_sgmii_82575; in igb_init_phy_params_82575()
198 phy->ops.reset = igb_phy_hw_reset; in igb_init_phy_params_82575()
206 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575; in igb_init_phy_params_82575()
207 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575; in igb_init_phy_params_82575()
209 switch (hw->mac.type) { in igb_init_phy_params_82575()
215 phy->ops.read_reg = igb_read_phy_reg_82580; in igb_init_phy_params_82575()
216 phy->ops.write_reg = igb_write_phy_reg_82580; in igb_init_phy_params_82575()
219 phy->ops.read_reg = igb_read_phy_reg_igp; in igb_init_phy_params_82575()
220 phy->ops.write_reg = igb_write_phy_reg_igp; in igb_init_phy_params_82575()
225 hw->bus.func = FIELD_GET(E1000_STATUS_FUNC_MASK, rd32(E1000_STATUS)); in igb_init_phy_params_82575()
227 /* Set phy->phy_addr and phy->id. */ in igb_init_phy_params_82575()
233 switch (phy->id) { in igb_init_phy_params_82575()
239 phy->type = e1000_phy_m88; in igb_init_phy_params_82575()
240 phy->ops.check_polarity = igb_check_polarity_m88; in igb_init_phy_params_82575()
241 phy->ops.get_phy_info = igb_get_phy_info_m88; in igb_init_phy_params_82575()
242 if (phy->id != M88E1111_I_PHY_ID) in igb_init_phy_params_82575()
243 phy->ops.get_cable_length = in igb_init_phy_params_82575()
246 phy->ops.get_cable_length = igb_get_cable_length_m88; in igb_init_phy_params_82575()
247 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; in igb_init_phy_params_82575()
249 if (phy->id == M88E1112_E_PHY_ID) { in igb_init_phy_params_82575()
252 ret_val = phy->ops.write_reg(hw, in igb_init_phy_params_82575()
258 ret_val = phy->ops.read_reg(hw, in igb_init_phy_params_82575()
268 hw->mac.ops.check_for_link = in igb_init_phy_params_82575()
271 if (phy->id == M88E1512_E_PHY_ID) { in igb_init_phy_params_82575()
276 if (phy->id == M88E1543_E_PHY_ID) { in igb_init_phy_params_82575()
283 phy->type = e1000_phy_igp_3; in igb_init_phy_params_82575()
284 phy->ops.get_phy_info = igb_get_phy_info_igp; in igb_init_phy_params_82575()
285 phy->ops.get_cable_length = igb_get_cable_length_igp_2; in igb_init_phy_params_82575()
286 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp; in igb_init_phy_params_82575()
287 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575; in igb_init_phy_params_82575()
288 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state; in igb_init_phy_params_82575()
292 phy->type = e1000_phy_82580; in igb_init_phy_params_82575()
293 phy->ops.force_speed_duplex = in igb_init_phy_params_82575()
295 phy->ops.get_cable_length = igb_get_cable_length_82580; in igb_init_phy_params_82575()
296 phy->ops.get_phy_info = igb_get_phy_info_82580; in igb_init_phy_params_82575()
297 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580; in igb_init_phy_params_82575()
298 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580; in igb_init_phy_params_82575()
301 phy->type = e1000_phy_i210; in igb_init_phy_params_82575()
302 phy->ops.check_polarity = igb_check_polarity_m88; in igb_init_phy_params_82575()
303 phy->ops.get_cfg_done = igb_get_cfg_done_i210; in igb_init_phy_params_82575()
304 phy->ops.get_phy_info = igb_get_phy_info_m88; in igb_init_phy_params_82575()
305 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2; in igb_init_phy_params_82575()
306 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580; in igb_init_phy_params_82575()
307 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580; in igb_init_phy_params_82575()
308 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; in igb_init_phy_params_82575()
311 phy->type = e1000_phy_bcm54616; in igb_init_phy_params_82575()
314 ret_val = -E1000_ERR_PHY; in igb_init_phy_params_82575()
323 * igb_init_nvm_params_82575 - Init NVM func ptrs.
328 struct e1000_nvm_info *nvm = &hw->nvm; in igb_init_nvm_params_82575()
334 /* Added to a constant, "size" becomes the left-shift value in igb_init_nvm_params_82575()
345 nvm->word_size = BIT(size); in igb_init_nvm_params_82575()
346 nvm->opcode_bits = 8; in igb_init_nvm_params_82575()
347 nvm->delay_usec = 1; in igb_init_nvm_params_82575()
349 switch (nvm->override) { in igb_init_nvm_params_82575()
351 nvm->page_size = 32; in igb_init_nvm_params_82575()
352 nvm->address_bits = 16; in igb_init_nvm_params_82575()
355 nvm->page_size = 8; in igb_init_nvm_params_82575()
356 nvm->address_bits = 8; in igb_init_nvm_params_82575()
359 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; in igb_init_nvm_params_82575()
360 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? in igb_init_nvm_params_82575()
364 if (nvm->word_size == BIT(15)) in igb_init_nvm_params_82575()
365 nvm->page_size = 128; in igb_init_nvm_params_82575()
367 nvm->type = e1000_nvm_eeprom_spi; in igb_init_nvm_params_82575()
370 nvm->ops.acquire = igb_acquire_nvm_82575; in igb_init_nvm_params_82575()
371 nvm->ops.release = igb_release_nvm_82575; in igb_init_nvm_params_82575()
372 nvm->ops.write = igb_write_nvm_spi; in igb_init_nvm_params_82575()
373 nvm->ops.validate = igb_validate_nvm_checksum; in igb_init_nvm_params_82575()
374 nvm->ops.update = igb_update_nvm_checksum; in igb_init_nvm_params_82575()
375 if (nvm->word_size < BIT(15)) in igb_init_nvm_params_82575()
376 nvm->ops.read = igb_read_nvm_eerd; in igb_init_nvm_params_82575()
378 nvm->ops.read = igb_read_nvm_spi; in igb_init_nvm_params_82575()
381 switch (hw->mac.type) { in igb_init_nvm_params_82575()
383 nvm->ops.validate = igb_validate_nvm_checksum_82580; in igb_init_nvm_params_82575()
384 nvm->ops.update = igb_update_nvm_checksum_82580; in igb_init_nvm_params_82575()
388 nvm->ops.validate = igb_validate_nvm_checksum_i350; in igb_init_nvm_params_82575()
389 nvm->ops.update = igb_update_nvm_checksum_i350; in igb_init_nvm_params_82575()
399 * igb_init_mac_params_82575 - Init MAC func ptrs.
404 struct e1000_mac_info *mac = &hw->mac; in igb_init_mac_params_82575()
405 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; in igb_init_mac_params_82575()
408 mac->mta_reg_count = 128; in igb_init_mac_params_82575()
410 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128; in igb_init_mac_params_82575()
412 switch (mac->type) { in igb_init_mac_params_82575()
414 mac->rar_entry_count = E1000_RAR_ENTRIES_82576; in igb_init_mac_params_82575()
417 mac->rar_entry_count = E1000_RAR_ENTRIES_82580; in igb_init_mac_params_82575()
421 mac->rar_entry_count = E1000_RAR_ENTRIES_I350; in igb_init_mac_params_82575()
424 mac->rar_entry_count = E1000_RAR_ENTRIES_82575; in igb_init_mac_params_82575()
428 if (mac->type >= e1000_82580) in igb_init_mac_params_82575()
429 mac->ops.reset_hw = igb_reset_hw_82580; in igb_init_mac_params_82575()
431 mac->ops.reset_hw = igb_reset_hw_82575; in igb_init_mac_params_82575()
433 if (mac->type >= e1000_i210) { in igb_init_mac_params_82575()
434 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210; in igb_init_mac_params_82575()
435 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210; in igb_init_mac_params_82575()
438 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575; in igb_init_mac_params_82575()
439 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575; in igb_init_mac_params_82575()
442 if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354)) in igb_init_mac_params_82575()
443 mac->ops.write_vfta = igb_write_vfta_i350; in igb_init_mac_params_82575()
445 mac->ops.write_vfta = igb_write_vfta; in igb_init_mac_params_82575()
448 mac->asf_firmware_present = true; in igb_init_mac_params_82575()
450 mac->arc_subsystem_valid = in igb_init_mac_params_82575()
454 if (mac->type >= e1000_i350) in igb_init_mac_params_82575()
455 dev_spec->eee_disable = false; in igb_init_mac_params_82575()
457 dev_spec->eee_disable = true; in igb_init_mac_params_82575()
459 if (mac->type >= e1000_i210) in igb_init_mac_params_82575()
460 dev_spec->clear_semaphore_once = true; in igb_init_mac_params_82575()
462 mac->ops.setup_physical_interface = in igb_init_mac_params_82575()
463 (hw->phy.media_type == e1000_media_type_copper) in igb_init_mac_params_82575()
467 if (mac->type == e1000_82580 || mac->type == e1000_i350) { in igb_init_mac_params_82575()
468 switch (hw->device_id) { in igb_init_mac_params_82575()
476 hw->dev_spec._82575.mas_capable = true; in igb_init_mac_params_82575()
484 * igb_set_sfp_media_type_82575 - derives SFP module media type.
494 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; in igb_set_sfp_media_type_82575()
495 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags; in igb_set_sfp_media_type_82575()
514 timeout--; in igb_set_sfp_media_type_82575()
528 dev_spec->module_plugged = true; in igb_set_sfp_media_type_82575()
529 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) { in igb_set_sfp_media_type_82575()
530 hw->phy.media_type = e1000_media_type_internal_serdes; in igb_set_sfp_media_type_82575()
531 } else if (eth_flags->e100_base_fx || eth_flags->e100_base_lx) { in igb_set_sfp_media_type_82575()
532 dev_spec->sgmii_active = true; in igb_set_sfp_media_type_82575()
533 hw->phy.media_type = e1000_media_type_internal_serdes; in igb_set_sfp_media_type_82575()
534 } else if (eth_flags->e1000_base_t) { in igb_set_sfp_media_type_82575()
535 dev_spec->sgmii_active = true; in igb_set_sfp_media_type_82575()
536 hw->phy.media_type = e1000_media_type_copper; in igb_set_sfp_media_type_82575()
538 hw->phy.media_type = e1000_media_type_unknown; in igb_set_sfp_media_type_82575()
543 hw->phy.media_type = e1000_media_type_unknown; in igb_set_sfp_media_type_82575()
554 struct e1000_mac_info *mac = &hw->mac; in igb_get_invariants_82575()
555 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; in igb_get_invariants_82575()
560 switch (hw->device_id) { in igb_get_invariants_82575()
564 mac->type = e1000_82575; in igb_get_invariants_82575()
574 mac->type = e1000_82576; in igb_get_invariants_82575()
586 mac->type = e1000_82580; in igb_get_invariants_82575()
592 mac->type = e1000_i350; in igb_get_invariants_82575()
600 mac->type = e1000_i210; in igb_get_invariants_82575()
603 mac->type = e1000_i211; in igb_get_invariants_82575()
608 mac->type = e1000_i354; in igb_get_invariants_82575()
611 return -E1000_ERR_MAC_INIT; in igb_get_invariants_82575()
619 * on the SGMII interface. For this, we'll set sgmii_active to true. in igb_get_invariants_82575()
621 hw->phy.media_type = e1000_media_type_copper; in igb_get_invariants_82575()
622 dev_spec->sgmii_active = false; in igb_get_invariants_82575()
623 dev_spec->module_plugged = false; in igb_get_invariants_82575()
628 switch (link_mode) { in igb_get_invariants_82575()
630 hw->phy.media_type = e1000_media_type_internal_serdes; in igb_get_invariants_82575()
635 hw->phy.media_type = e1000_media_type_copper; in igb_get_invariants_82575()
636 dev_spec->sgmii_active = true; in igb_get_invariants_82575()
639 fallthrough; /* for I2C based SGMII */ in igb_get_invariants_82575()
644 (hw->phy.media_type == e1000_media_type_unknown)) { in igb_get_invariants_82575()
648 hw->phy.media_type = e1000_media_type_internal_serdes; in igb_get_invariants_82575()
651 hw->phy.media_type = e1000_media_type_copper; in igb_get_invariants_82575()
652 dev_spec->sgmii_active = true; in igb_get_invariants_82575()
661 if (dev_spec->sgmii_active) in igb_get_invariants_82575()
680 switch (hw->mac.type) { in igb_get_invariants_82575()
692 /* if part supports SR-IOV then initialize mailbox parameters */ in igb_get_invariants_82575()
693 switch (mac->type) { in igb_get_invariants_82575()
710 * igb_acquire_phy_82575 - Acquire rights to access PHY
720 if (hw->bus.func == E1000_FUNC_1) in igb_acquire_phy_82575()
722 else if (hw->bus.func == E1000_FUNC_2) in igb_acquire_phy_82575()
724 else if (hw->bus.func == E1000_FUNC_3) in igb_acquire_phy_82575()
727 return hw->mac.ops.acquire_swfw_sync(hw, mask); in igb_acquire_phy_82575()
731 * igb_release_phy_82575 - Release rights to access PHY
741 if (hw->bus.func == E1000_FUNC_1) in igb_release_phy_82575()
743 else if (hw->bus.func == E1000_FUNC_2) in igb_release_phy_82575()
745 else if (hw->bus.func == E1000_FUNC_3) in igb_release_phy_82575()
748 hw->mac.ops.release_swfw_sync(hw, mask); in igb_release_phy_82575()
752 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
763 s32 ret_val = -E1000_ERR_PARAM; in igb_read_phy_reg_sgmii_82575()
770 ret_val = hw->phy.ops.acquire(hw); in igb_read_phy_reg_sgmii_82575()
776 hw->phy.ops.release(hw); in igb_read_phy_reg_sgmii_82575()
783 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
794 s32 ret_val = -E1000_ERR_PARAM; in igb_write_phy_reg_sgmii_82575()
802 ret_val = hw->phy.ops.acquire(hw); in igb_write_phy_reg_sgmii_82575()
808 hw->phy.ops.release(hw); in igb_write_phy_reg_sgmii_82575()
815 * igb_get_phy_id_82575 - Retrieve PHY addr and id
823 struct e1000_phy_info *phy = &hw->phy; in igb_get_phy_id_82575()
830 if (hw->mac.type == e1000_i354) in igb_get_phy_id_82575()
833 /* For SGMII PHYs, we try the list of possible addresses until in igb_get_phy_id_82575()
834 * we find one that works. For non-SGMII PHYs in igb_get_phy_id_82575()
836 * work. The result of this function should mean phy->phy_addr in igb_get_phy_id_82575()
837 * and phy->id are set correctly. in igb_get_phy_id_82575()
840 phy->addr = 1; in igb_get_phy_id_82575()
846 switch (hw->mac.type) { in igb_get_phy_id_82575()
851 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT; in igb_get_phy_id_82575()
860 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; in igb_get_phy_id_82575()
863 ret_val = -E1000_ERR_PHY; in igb_get_phy_id_82575()
870 /* Power on sgmii phy if it is disabled */ in igb_get_phy_id_82575()
877 * Therefore, we need to test 1-7 in igb_get_phy_id_82575()
879 for (phy->addr = 1; phy->addr < 8; phy->addr++) { in igb_get_phy_id_82575()
882 hw_dbg("Vendor ID 0x%08X read at address %u\n", in igb_get_phy_id_82575()
883 phy_id, phy->addr); in igb_get_phy_id_82575()
885 * the only supported SGMII PHY product. in igb_get_phy_id_82575()
890 hw_dbg("PHY address %u was unreadable\n", phy->addr); in igb_get_phy_id_82575()
895 if (phy->addr == 8) { in igb_get_phy_id_82575()
896 phy->addr = 0; in igb_get_phy_id_82575()
897 ret_val = -E1000_ERR_PHY; in igb_get_phy_id_82575()
911 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
918 struct e1000_phy_info *phy = &hw->phy; in igb_phy_hw_reset_sgmii_82575()
925 hw_dbg("Soft resetting SGMII attached PHY...\n"); in igb_phy_hw_reset_sgmii_82575()
928 * to work on SGMII. No further documentation is given. in igb_phy_hw_reset_sgmii_82575()
930 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); in igb_phy_hw_reset_sgmii_82575()
938 if (phy->id == M88E1512_E_PHY_ID) in igb_phy_hw_reset_sgmii_82575()
940 if (phy->id == M88E1543_E_PHY_ID) in igb_phy_hw_reset_sgmii_82575()
947 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
961 struct e1000_phy_info *phy = &hw->phy; in igb_set_d0_lplu_state_82575()
965 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); in igb_set_d0_lplu_state_82575()
971 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, in igb_set_d0_lplu_state_82575()
977 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, in igb_set_d0_lplu_state_82575()
980 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, in igb_set_d0_lplu_state_82575()
986 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, in igb_set_d0_lplu_state_82575()
993 if (phy->smart_speed == e1000_smart_speed_on) { in igb_set_d0_lplu_state_82575()
994 ret_val = phy->ops.read_reg(hw, in igb_set_d0_lplu_state_82575()
1000 ret_val = phy->ops.write_reg(hw, in igb_set_d0_lplu_state_82575()
1004 } else if (phy->smart_speed == e1000_smart_speed_off) { in igb_set_d0_lplu_state_82575()
1005 ret_val = phy->ops.read_reg(hw, in igb_set_d0_lplu_state_82575()
1011 ret_val = phy->ops.write_reg(hw, in igb_set_d0_lplu_state_82575()
1023 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
1037 struct e1000_phy_info *phy = &hw->phy; in igb_set_d0_lplu_state_82580()
1055 if (phy->smart_speed == e1000_smart_speed_on) in igb_set_d0_lplu_state_82580()
1057 else if (phy->smart_speed == e1000_smart_speed_off) in igb_set_d0_lplu_state_82580()
1065 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
1080 struct e1000_phy_info *phy = &hw->phy; in igb_set_d3_lplu_state_82580()
1092 if (phy->smart_speed == e1000_smart_speed_on) in igb_set_d3_lplu_state_82580()
1094 else if (phy->smart_speed == e1000_smart_speed_off) in igb_set_d3_lplu_state_82580()
1096 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || in igb_set_d3_lplu_state_82580()
1097 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || in igb_set_d3_lplu_state_82580()
1098 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { in igb_set_d3_lplu_state_82580()
1109 * igb_acquire_nvm_82575 - Request for access to EEPROM
1115 * EEPROM access and return -E1000_ERR_NVM (-1).
1121 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM); in igb_acquire_nvm_82575()
1128 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM); in igb_acquire_nvm_82575()
1135 * igb_release_nvm_82575 - Release exclusive access to EEPROM
1144 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM); in igb_release_nvm_82575()
1148 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1165 ret_val = -E1000_ERR_SWFW_SYNC; in igb_acquire_swfw_sync_82575()
1183 ret_val = -E1000_ERR_SWFW_SYNC; in igb_acquire_swfw_sync_82575()
1197 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
1219 * igb_get_cfg_done_82575 - Read config done bit
1223 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1225 * 0. If we were to return with error, EEPROM-less silicon
1233 if (hw->bus.func == 1) in igb_get_cfg_done_82575()
1235 else if (hw->bus.func == E1000_FUNC_2) in igb_get_cfg_done_82575()
1237 else if (hw->bus.func == E1000_FUNC_3) in igb_get_cfg_done_82575()
1244 timeout--; in igb_get_cfg_done_82575()
1251 (hw->phy.type == e1000_phy_igp_3)) in igb_get_cfg_done_82575()
1258 * igb_get_link_up_info_82575 - Get link speed/duplex info
1272 if (hw->phy.media_type != e1000_media_type_copper) in igb_get_link_up_info_82575()
1283 * igb_check_for_link_82575 - Check for link
1286 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1294 if (hw->phy.media_type != e1000_media_type_copper) { in igb_check_for_link_82575()
1301 hw->mac.get_link_status = !hw->mac.serdes_has_link; in igb_check_for_link_82575()
1303 /* Configure Flow Control now that Auto-Neg has completed. in igb_check_for_link_82575()
1305 * settings because we may have had to re-autoneg with a in igb_check_for_link_82575()
1319 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1327 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && in igb_power_up_serdes_link_82575()
1347 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1352 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1358 struct e1000_mac_info *mac = &hw->mac; in igb_get_pcs_speed_and_duplex_82575()
1362 mac->serdes_has_link = false; in igb_get_pcs_speed_and_duplex_82575()
1366 /* Read the PCS Status register for link state. For non-copper mode, in igb_get_pcs_speed_and_duplex_82575()
1377 mac->serdes_has_link = true; in igb_get_pcs_speed_and_duplex_82575()
1394 if (mac->type == e1000_i354) { in igb_get_pcs_speed_and_duplex_82575()
1411 * igb_shutdown_serdes_link_82575 - Remove link during power down
1421 if (hw->phy.media_type != e1000_media_type_internal_serdes && in igb_shutdown_serdes_link_82575()
1443 * igb_reset_hw_82575 - Reset hardware
1454 /* Prevent the PCI-E bus from sticking if there is no TLP connection in igb_reset_hw_82575()
1459 hw_dbg("PCI-E Master disable polling has failed.\n"); in igb_reset_hw_82575()
1464 hw_dbg("PCI-E Set completion timeout has failed.\n"); in igb_reset_hw_82575()
1504 * igb_init_hw_82575 - Initialize hardware
1511 struct e1000_mac_info *mac = &hw->mac; in igb_init_hw_82575()
1513 u16 i, rar_count = mac->rar_entry_count; in igb_init_hw_82575()
1515 if ((hw->mac.type >= e1000_i210) && in igb_init_hw_82575()
1538 for (i = 0; i < mac->mta_reg_count; i++) in igb_init_hw_82575()
1543 for (i = 0; i < mac->uta_reg_count; i++) in igb_init_hw_82575()
1559 * igb_setup_copper_link_82575 - Configure copper link settings
1562 * Configures the link for auto-neg or forced speed and duplex. Then we check
1578 switch (hw->mac.type) { in igb_setup_copper_link_82575()
1595 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) { in igb_setup_copper_link_82575()
1599 ret_val = hw->phy.ops.reset(hw); in igb_setup_copper_link_82575()
1605 switch (hw->phy.type) { in igb_setup_copper_link_82575()
1608 switch (hw->phy.id) { in igb_setup_copper_link_82575()
1631 ret_val = -E1000_ERR_PHY; in igb_setup_copper_link_82575()
1644 * igb_setup_serdes_link_82575 - Setup link for serdes
1647 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1649 * interface (sgmii), or serdes fiber is being used. Configures the link
1650 * for auto-negotiation or forces speed/duplex.
1659 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && in igb_setup_serdes_link_82575()
1680 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) { in igb_setup_serdes_link_82575()
1684 /* Set switch control to serdes energy detect */ in igb_setup_serdes_link_82575()
1693 pcs_autoneg = hw->mac.autoneg; in igb_setup_serdes_link_82575()
1695 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { in igb_setup_serdes_link_82575()
1697 /* sgmii mode lets the phy handle forcing speed/duplex */ in igb_setup_serdes_link_82575()
1699 /* autoneg time out should be disabled for SGMII mode */ in igb_setup_serdes_link_82575()
1707 if (hw->mac.type == e1000_82575 || in igb_setup_serdes_link_82575()
1708 hw->mac.type == e1000_82576) { in igb_setup_serdes_link_82575()
1709 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data); in igb_setup_serdes_link_82575()
1719 /* non-SGMII modes only supports a speed of 1000/Full for the in igb_setup_serdes_link_82575()
1752 switch (hw->fc.requested_mode) { in igb_setup_serdes_link_82575()
1766 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); in igb_setup_serdes_link_82575()
1774 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); in igb_setup_serdes_link_82575()
1786 * igb_sgmii_active_82575 - Return sgmii state
1789 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1791 * return the current state of the sgmii interface.
1795 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; in igb_sgmii_active_82575()
1796 return dev_spec->sgmii_active; in igb_sgmii_active_82575()
1800 * igb_reset_init_script_82575 - Inits HW defaults after reset
1808 if (hw->mac.type == e1000_82575) { in igb_reset_init_script_82575()
1836 * igb_read_mac_addr_82575 - Read device MAC address
1858 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1872 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1929 if (hw->phy.media_type == e1000_media_type_internal_serdes || in igb_clear_hw_cntrs_82575()
1935 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1953 if (hw->mac.type != e1000_82575 || in igb_rx_fifo_flush_82575()
2012 * igb_set_pcie_completion_timeout - set pci-e completion timeout
2017 * than the 10ms recommended by the pci-e spec. To address this we need to
2061 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2064 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2066 * enables/disables L2 switch anti-spoofing functionality.
2072 switch (hw->mac.type) { in igb_vmdq_set_anti_spoofing_pf()
2088 /* The PF can spoof - it has to in order to in igb_vmdq_set_anti_spoofing_pf()
2100 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
2104 * enables/disables L2 switch loopback functionality.
2110 switch (hw->mac.type) { in igb_vmdq_set_loopback_pf()
2136 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
2155 * igb_read_phy_reg_82580 - Read 82580 MDI control register
2167 ret_val = hw->phy.ops.acquire(hw); in igb_read_phy_reg_82580()
2173 hw->phy.ops.release(hw); in igb_read_phy_reg_82580()
2180 * igb_write_phy_reg_82580 - Write 82580 MDI control register
2192 ret_val = hw->phy.ops.acquire(hw); in igb_write_phy_reg_82580()
2198 hw->phy.ops.release(hw); in igb_write_phy_reg_82580()
2205 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2218 if (hw->mac.type != e1000_82580) in igb_reset_mdicnfg_82580()
2223 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + in igb_reset_mdicnfg_82580()
2224 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, in igb_reset_mdicnfg_82580()
2242 * igb_reset_hw_82580 - Reset hardware
2254 bool global_device_reset = hw->dev_spec._82575.global_device_reset; in igb_reset_hw_82580()
2256 hw->dev_spec._82575.global_device_reset = false; in igb_reset_hw_82580()
2261 if (hw->mac.type == e1000_82580) in igb_reset_hw_82580()
2267 /* Prevent the PCI-E bus from sticking if there is no TLP connection in igb_reset_hw_82580()
2272 hw_dbg("PCI-E Master disable polling has failed.\n"); in igb_reset_hw_82580()
2284 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask)) in igb_reset_hw_82580()
2325 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask); in igb_reset_hw_82580()
2331 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2351 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
2367 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); in igb_validate_nvm_checksum_with_offset()
2377 ret_val = -E1000_ERR_NVM; in igb_validate_nvm_checksum_with_offset()
2386 * igb_update_nvm_checksum_with_offset - Update EEPROM
2402 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); in igb_update_nvm_checksum_with_offset()
2409 checksum = (u16) NVM_SUM - checksum; in igb_update_nvm_checksum_with_offset()
2410 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1, in igb_update_nvm_checksum_with_offset()
2420 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2434 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); in igb_validate_nvm_checksum_82580()
2460 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
2473 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); in igb_update_nvm_checksum_82580()
2482 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1, in igb_update_nvm_checksum_82580()
2502 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2528 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
2553 * __igb_access_emi_reg - Read/write EMI register
2564 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address); in __igb_access_emi_reg()
2569 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data); in __igb_access_emi_reg()
2571 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data); in __igb_access_emi_reg()
2577 * igb_read_emi_reg - Read Extended Management Interface register
2588 * igb_set_eee_i350 - Enable/disable EEE support
2600 if ((hw->mac.type < e1000_i350) || in igb_set_eee_i350()
2601 (hw->phy.media_type != e1000_media_type_copper)) in igb_set_eee_i350()
2607 if (!(hw->dev_spec._82575.eee_disable)) { in igb_set_eee_i350()
2644 * igb_set_eee_i354 - Enable/disable EEE support
2654 struct e1000_phy_info *phy = &hw->phy; in igb_set_eee_i354()
2658 if ((hw->phy.media_type != e1000_media_type_copper) || in igb_set_eee_i354()
2659 ((phy->id != M88E1543_E_PHY_ID) && in igb_set_eee_i354()
2660 (phy->id != M88E1512_E_PHY_ID))) in igb_set_eee_i354()
2663 if (!hw->dev_spec._82575.eee_disable) { in igb_set_eee_i354()
2664 /* Switch to PHY page 18. */ in igb_set_eee_i354()
2665 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18); in igb_set_eee_i354()
2669 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1, in igb_set_eee_i354()
2675 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1, in igb_set_eee_i354()
2681 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); in igb_set_eee_i354()
2725 * igb_get_eee_status_i354 - Get EEE status
2734 struct e1000_phy_info *phy = &hw->phy; in igb_get_eee_status_i354()
2739 if ((hw->phy.media_type != e1000_media_type_copper) || in igb_get_eee_status_i354()
2740 ((phy->id != M88E1543_E_PHY_ID) && in igb_get_eee_status_i354()
2741 (phy->id != M88E1512_E_PHY_ID))) in igb_get_eee_status_i354()
2772 * igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2786 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; in igb_get_thermal_sensor_data_generic()
2788 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0)) in igb_get_thermal_sensor_data_generic()
2791 data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF); in igb_get_thermal_sensor_data_generic()
2794 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset); in igb_get_thermal_sensor_data_generic()
2798 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg); in igb_get_thermal_sensor_data_generic()
2808 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor); in igb_get_thermal_sensor_data_generic()
2813 hw->phy.ops.read_i2c_byte(hw, in igb_get_thermal_sensor_data_generic()
2816 &data->sensor[i].temp); in igb_get_thermal_sensor_data_generic()
2822 * igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2839 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; in igb_init_thermal_sensor_thresh_generic()
2841 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0)) in igb_init_thermal_sensor_thresh_generic()
2846 data->sensor[0].location = 0x1; in igb_init_thermal_sensor_thresh_generic()
2847 data->sensor[0].caution_thresh = in igb_init_thermal_sensor_thresh_generic()
2849 data->sensor[0].max_op_thresh = in igb_init_thermal_sensor_thresh_generic()
2853 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset); in igb_init_thermal_sensor_thresh_generic()
2857 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg); in igb_init_thermal_sensor_thresh_generic()
2866 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor); in igb_init_thermal_sensor_thresh_generic()
2871 hw->phy.ops.write_i2c_byte(hw, in igb_init_thermal_sensor_thresh_generic()
2877 data->sensor[i].location = sensor_location; in igb_init_thermal_sensor_thresh_generic()
2878 data->sensor[i].caution_thresh = therm_limit; in igb_init_thermal_sensor_thresh_generic()
2879 data->sensor[i].max_op_thresh = therm_limit - in igb_init_thermal_sensor_thresh_generic()