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/linux-6.12.1/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_catalog.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
17 * 5 ctl paths. In all cases, it can have max 12 hardware blocks
52 * SSPP sub-blocks/features
54 …* @DPU_SSPP_SCALER_QSEED3_COMPATIBLE, QSEED3-compatible alogorithm support (includes QSEED3, QSEE…
57 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion
60 * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control
90 * MIXER sub-blocks/features
92 * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration
[all …]
Ddpu_hw_catalog.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
271 * SSPP sub blocks config
369 * MIXER sub blocks config
415 * DSPP sub blocks config
428 * PINGPONG sub blocks config
448 * DSC sub blocks config
471 * VBIF sub blocks config
/linux-6.12.1/arch/arm64/crypto/
Daes-modes.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm64/crypto/aes-modes.S - chaining mode wrappers for AES
5 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
8 /* included by aes-ce.S and aes-neon.S */
49 * int blocks)
51 * int blocks)
62 ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 pt blocks */
66 st1 {v0.16b-v3.16b}, [x0], #64
92 ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 ct blocks */
96 st1 {v0.16b-v3.16b}, [x0], #64
[all …]
Dghash-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 - 2018 Linaro Ltd. <ard.biesheuvel@linaro.org>
61 .arch armv8-a+crypto
149 ld1 {HH.2d-HH4.2d}, [x8]
197 // PMULL (64x64->128) based reduction for CPUs that can do
214 // 64x64->128 PMULL instruction
253 tbnz w0, #0, 2f // skip until #blocks is a
256 1: ld1 {XM3.16b-TT4.16b}, [x2], #64
258 sub w0, w0, #4
320 sub w0, w0, #1
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/linux-6.12.1/fs/xfs/scrub/
Dbitmap.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2018-2023 Oracle. All Rights Reserved.
36 #define START(node) ((node)->bn_start)
37 #define LAST(node) ((node)->bn_last)
41 * forward-declare them anyway for clarity.
63 for ((bn) = rb_entry_safe(rb_first(&(bitmap)->xb_root.rb_root), \ in INTERVAL_TREE_DEFINE()
66 (bn) = rb_entry_safe(rb_next(&(bn)->bn_rbnode), \
78 uint64_t last = start + len - 1;
80 while ((bn = xbitmap64_tree_iter_first(&bitmap->xb_root, start, last))) {
81 if (bn->bn_start < start && bn->bn_last > last) {
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Drepair.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2018-2023 Oracle. All Rights Reserved.
50 * told us to fix it. This function returns -EAGAIN to mean "re-run scrub",
61 trace_xrep_attempt(XFS_I(file_inode(sc->file)), sc->sm, error); in xrep_attempt()
63 xchk_ag_btcur_free(&sc->sa); in xrep_attempt()
66 ASSERT(sc->ops->repair); in xrep_attempt()
67 run->repair_attempted = true; in xrep_attempt()
69 error = sc->ops->repair(sc); in xrep_attempt()
70 trace_xrep_done(XFS_I(file_inode(sc->file)), sc->sm, error); in xrep_attempt()
71 run->repair_ns += xchk_stats_elapsed_ns(repair_start); in xrep_attempt()
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Dreap.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2022-2023 Oracle. All Rights Reserved.
46 * Disposal of Blocks from Old Metadata
49 * to dispose of the blocks that (we think) the old btree was using.
52 * blocks with the same rmap owner that are owned by another data structure
54 * remaining in bitmap are the old btree's blocks.
57 * blocks on disk. The rmap data can tell us if there are multiple owners, so
64 * will be rebuilt (atop different blocks), thereby removing all the cross
126 error = xfs_rmap_alloc(sc->tp, sc->sa.agf_bp, sc->sa.pag, agbno, 1, in xreap_put_freelist()
132 error = xfs_alloc_read_agfl(sc->sa.pag, sc->tp, &agfl_bp); in xreap_put_freelist()
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/linux-6.12.1/include/linux/mfd/
Drohm-bd957x.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
17 * The BD9576 has own IRQ 'blocks' for:
18 * - I2C/thermal,
19 * - Over voltage protection
20 * - Short-circuit protection
21 * - Over current protection
22 * - Over voltage detection
23 * - Under voltage detection
24 * - Under voltage protection
25 * - 'system interrupt'.
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/linux-6.12.1/Documentation/devicetree/bindings/interconnect/
Dsamsung,exynos-bus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
15 sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
20 sub-blocks.
22 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
24 line. The power line might be shared among one more sub-blocks. So, we can
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/linux-6.12.1/lib/zstd/compress/
Dzstd_compress_superblock.c5 * This source code is licensed under both the BSD-style license (found in the
8 * You may select, at your option, one of the above-listed licenses.
11 /*-*************************************
23 * Compresses literals section for a sub-block.
32 * hufMetadata->hType has literals block type info.
33 * If it is set_basic, all sub-blocks literals section will be Raw_Literals_Block.
34 * If it is set_rle, all sub-blocks literals section will be RLE_Literals_Block.
35 …* If it is set_compressed, first sub-block's literals section will be Compressed_Literals_Blo…
36 * If it is set_compressed, first sub-block's literals section will be Treeless_Literals_Block
37 * and the following sub-blocks' literals sections will be Treeless_Literals_Block.
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/linux-6.12.1/arch/arm/crypto/
Daes-neonbs-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
11 * 'Faster and Timing-Attack Resistant AES-GCM' by Emilia Kaesper and
15 * for 32-bit ARM written by Andy Polyakov <appro@openssl.org>
262 vld1.8 {\t0-\t1}, [bskey, :256]!
264 vld1.8 {\t2-\t3}, [bskey, :256]!
269 vld1.8 {\t0-\t1}, [bskey, :256]!
273 vld1.8 {\t2-\t3}, [bskey, :256]!
354 vld1.8 {\t0-\t1}, [bskey, :256]!
356 vld1.8 {\t2-\t3}, [bskey, :256]!
358 vld1.8 {\t4-\t5}, [bskey, :256]!
[all …]
Daes-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * aes-ce-core.S - AES in CBC/CTR/XTS mode using ARMv8 Crypto Extensions
12 .arch armv8-a
13 .fpu crypto-neon-fp-armv8
102 vld1.32 {q10-q11}, [ip]!
104 vld1.32 {q12-q13}, [ip]!
106 vld1.32 {q10-q11}, [ip]!
108 vld1.32 {q12-q13}, [ip]!
110 blo 0f @ AES-128: 10 rounds
111 vld1.32 {q10-q11}, [ip]!
[all …]
/linux-6.12.1/arch/x86/crypto/
Daes-gcm-aesni-x86_64.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // AES-NI optimized AES-GCM for x86_64
9 //------------------------------------------------------------------------------
11 // This file is dual-licensed, meaning that you can use it under your choice of
17 // http://www.apache.org/licenses/LICENSE-2.0
49 //------------------------------------------------------------------------------
51 // This file implements AES-GCM (Galois/Counter Mode) for x86_64 CPUs that
52 // support the original set of AES instructions, i.e. AES-NI. Two
55 // that the AVX implementation takes advantage of VEX-coded instructions in some
57 // implementation does *not* use 256-bit vectors, as AES is not supported on
[all …]
Daes-xts-avx-x86_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * AES-XTS for modern x86_64 CPUs
11 * This file implements AES-XTS for modern x86_64 CPUs. To handle the
16 * AES-NI + AVX
17 * - 128-bit vectors (1 AES block per vector)
18 * - VEX-coded instructions
19 * - xmm0-xmm15
20 * - This is for older CPUs that lack VAES but do have AVX.
23 * - 256-bit vectors (2 AES blocks per vector)
24 * - VEX-coded instructions
[all …]
Dchacha-avx512vl-x86_64.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * ChaCha 256-bit cipher algorithm, x64 AVX-512VL functions
29 # %rsi: up to 2 data blocks output, o
30 # %rdx: up to 2 data blocks input, i
34 # This function encrypts two ChaCha blocks by loading the state
41 # x0..3[0-2] = s0..3
110 sub $2,%r8d
181 sub $1,%rax
194 # %rsi: up to 4 data blocks output, o
195 # %rdx: up to 4 data blocks input, i
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Daes-gcm-avx10-x86_64.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // VAES and VPCLMULQDQ optimized AES-GCM for x86_64
9 //------------------------------------------------------------------------------
11 // This file is dual-licensed, meaning that you can use it under your choice of
17 // http://www.apache.org/licenses/LICENSE-2.0
49 //------------------------------------------------------------------------------
51 // This file implements AES-GCM (Galois/Counter Mode) for x86_64 CPUs that
54 // decryption update functions which are the most performance-critical, are
55 // provided in two variants generated from a macro: one using 256-bit vectors
56 // (suffix: vaes_avx10_256) and one using 512-bit vectors (vaes_avx10_512). The
[all …]
/linux-6.12.1/arch/riscv/crypto/
Daes-riscv64-zvkned.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // This file is dual-licensed, meaning that you can use it under your
41 // The generated code of this file depends on the following RISC-V extensions:
42 // - RV64I
43 // - RISC-V Vector ('V') with VLEN >= 128
44 // - RISC-V Vector AES block cipher extension ('Zvkned')
51 #include "aes-macros.S"
88 // t0 is the remaining length in 32-bit words. It's a multiple of 4.
91 sub t0, t0, t1 // Subtract number of words processed
134 addi LEN, LEN, -16
[all …]
Daes-riscv64-zvkned-zvkb.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // This file is dual-licensed, meaning that you can use it under your
39 // The generated code of this file depends on the following RISC-V extensions:
40 // - RV64I
41 // - RISC-V Vector ('V') with VLEN >= 128
42 // - RISC-V Vector AES block cipher extension ('Zvkned')
43 // - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb')
50 #include "aes-macros.S"
63 // LEN32 = number of blocks, rounded up, in 32-bit words.
68 // Create a mask that selects the last 32-bit word of each 128-bit
[all …]
/linux-6.12.1/Documentation/filesystems/
Dzonefs.rst1 .. SPDX-License-Identifier: GPL-2.0
4 ZoneFS - Zone filesystem for Zoned block devices
11 as a file. Unlike a regular POSIX-compliant file system with native zoned block
18 than to a full-featured POSIX file system. The goal of zonefs is to simplify
22 example of this approach is the implementation of LSM (log-structured merge)
31 -------------------
62 by sub-directories. This file structure is built entirely using zone information
63 provided by the device and so does not require any complex on-disk metadata
66 On-disk metadata
67 ----------------
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/linux-6.12.1/Documentation/devicetree/bindings/reset/
Dreset.txt8 Hardware blocks typically receive a reset signal. This signal is generated by
10 reset consumer (the module being reset, or a module managing when a sub-
15 specifier - a list of DT cells that represents the reset signal within the
21 in hardware for a reset signal to affect multiple logically separate HW blocks
35 #reset-cells: Number of cells in a reset specifier; Typically 0 for nodes
41 rst: reset-controller {
42 #reset-cells = <1>;
51 #reset-cells, then only the phandle portion of the pair will
55 reset-names: List of reset signal name strings sorted in the same order as
56 the resets property. Consumers drivers will use reset-names to
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/linux-6.12.1/Documentation/driver-api/media/
Dv4l2-intro.rst1 .. SPDX-License-Identifier: GPL-2.0
4 ------------
8 /dev, and create also non-V4L2 devices such as DVB, ALSA, FB, I2C and input
15 called 'sub-devices'.
22 connecting to sub-devices themselves. Some of this is quite complicated
28 So this framework sets up the basic building blocks that all drivers
32 A good example to look at as a reference is the v4l2-pci-skeleton.c
38 -------------------------
44 2) A way of initializing and commanding sub-devices (if any).
47 and keeping track of device-node specific data.
[all …]
/linux-6.12.1/Documentation/admin-guide/media/
Dipu3.rst1 .. SPDX-License-Identifier: GPL-2.0
24 ImgU). The CIO2 driver is available as drivers/media/pci/intel/ipu3/ipu3-cio2*
36 Both of the drivers implement V4L2, Media Controller and V4L2 sub-device
38 MIPI CSI-2 interfaces through V4L2 sub-device sensor drivers.
44 interface to the user space. There is a video node for each CSI-2 receiver,
47 The CIO2 contains four independent capture channel, each with its own MIPI CSI-2
48 receiver and DMA engine. Each channel is modelled as a V4L2 sub-device exposed
49 to userspace as a V4L2 sub-device node and has two pads:
53 .. flat-table::
54 :header-rows: 1
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dst,stm32-sai.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/st,stm32-sai.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Olivier Moysan <olivier.moysan@foss.st.com>
14 protocols as I2S standards, LSB or MSB-justified, PCM/DSP, TDM, and AC'97.
15 The SAI contains two independent audio sub-blocks. Each sub-block has
21 - st,stm32f4-sai
22 - st,stm32h7-sai
26 - description: Base address and size of SAI common register set.
[all …]
/linux-6.12.1/drivers/gpu/drm/msm/
DNOTES4 display controller blocks at play:
5 + MDP3 - ?? seems to be what is on geeksphone peak device
6 + MDP4 - S3 (APQ8060, touchpad), S4-pro (APQ8064, nexus4 & ifc6410)
7 + MDP5 - snapdragon 800
12 Plus a handful of blocks around them for HDMI/DSI/etc output.
18 But, HDMI/DSI/etc blocks seem like they can be shared across multiple
19 display controller blocks. And I for sure don't want to have to deal
20 with N different kms devices from xf86-video-freedreno. Plus, it
27 And one or more 'struct msm_gpu' for the various different gpu sub-
38 plane -> PIPE{RGBn,VGn} \
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/linux-6.12.1/Documentation/filesystems/ext4/
Dinodes.rst1 .. SPDX-License-Identifier: GPL-2.0
4 -----------
15 links and is in general more seek-happy than ext4 due to its simpler
19 sized to have enough blocks to store at least
22 ``(inode_number - 1) / sb.s_inodes_per_group``, and the offset into the
23 group's table is ``(inode_number - 1) % sb.s_inodes_per_group``. There
31 .. list-table::
33 :header-rows: 1
36 * - Offset
37 - Size
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