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/linux-6.12.1/drivers/spi/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # SPI driver configuration
5 menuconfig SPI config
6 bool "SPI support"
10 protocol. Chips that support SPI can have data transfer rates
12 controller and a chipselect. Most SPI slaves don't support
13 dynamic device discovery; some are even write-only or read-only.
15 SPI is widely used by microcontrollers to talk with sensors,
17 chips, analog to digital (and d-to-a) converters, and more.
18 MMC and SD cards can be accessed using SPI protocol; and for
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Dspi-lantiq-ssc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011-2015 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
4 * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
20 #include <linux/spi/spi.h>
54 #define LTQ_SPI_CLC_SMC_S 16 /* Clock divider for sleep mode */
56 #define LTQ_SPI_CLC_RMC_S 8 /* Clock divider for normal run mode */
71 #define LTQ_SPI_CON_EM BIT(24) /* Echo mode */
94 #define LTQ_SPI_STAT_ME BIT(7) /* Mode error flag */
109 #define LTQ_SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */
110 #define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */
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Dspi-gpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * SPI host driver using generic bitbanged GPIO
15 #include <linux/spi/spi.h>
16 #include <linux/spi/spi_bitbang.h>
17 #include <linux/spi/spi_gpio.h>
20 * This bitbanging SPI host driver should help make systems usable
21 * when a native hardware SPI engine is not available, perhaps because
25 * platform_device->driver_data ... points to spi_gpio
27 * spi->controller_state ... reserved for bitbang framework code
29 * spi->controller->dev.driver_data ... points to spi_gpio->bitbang
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Dspi-sifive.c1 // SPDX-License-Identifier: GPL-2.0
5 // SiFive SPI controller driver (master mode only)
15 #include <linux/spi/spi.h>
27 #define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */
30 #define SIFIVE_SPI_REG_CSMODE 0x18 /* Chip select mode */
38 #define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control */
39 #define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction format */
96 struct completion done; /* wake-up from interrupt */
99 static void sifive_spi_write(struct sifive_spi *spi, int offset, u32 value) in sifive_spi_write() argument
101 iowrite32(value, spi->regs + offset); in sifive_spi_write()
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Dspi-omap2-mcspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/dma-mapping.h>
28 #include <linux/spi/spi.h>
32 #include <linux/platform_data/spi-omap2-mcspi.h>
49 /* per-channel banks, 0x14 bytes each, first is: */
56 /* per-register bitmasks: */
143 u16 mode; member
154 writel_relaxed(val, mcspi->base + idx); in mcspi_write_reg()
161 return readl_relaxed(mcspi->base + idx); in mcspi_read_reg()
164 static inline void mcspi_write_cs_reg(const struct spi_device *spi, in mcspi_write_cs_reg() argument
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Dspi-stm32.c1 // SPDX-License-Identifier: GPL-2.0
3 // STMicroelectronics STM32 SPI Controller driver
5 // Copyright (C) 2017, STMicroelectronics - All Rights Reserved
21 #include <linux/spi/spi.h>
25 /* STM32F4/7 SPI registers */
81 /* STM32F4 SPI Baud Rate min/max divisor */
85 /* STM32H7 SPI registers */
157 /* STM32MP25 SPI registers bit fields */
171 /* STM32H7 SPI Master Baud Rate min/max divisor */
175 /* STM32H7 SPI Communication mode */
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Dspi-fsl-spi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale SPI controller driver.
10 * CPM SPI and QE buffer descriptors mode support:
19 #include <linux/dma-mapping.h>
33 #include <linux/spi/spi.h>
34 #include <linux/spi/spi_bitbang.h>
45 #include "spi-fsl-lib.h"
46 #include "spi-fsl-cpm.h"
47 #include "spi-fsl-spi.h"
66 .compatible = "fsl,spi",
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Dspi-ppc4xx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SPI_PPC4XX SPI controller driver.
9 * Based in part on drivers/spi/spi_s3c24xx.c
17 * The PPC4xx SPI controller has no FIFO so each sent/received byte will
20 * during SPI transfers by setting max_speed_hz via the device tree.
35 #include <linux/spi/spi.h>
36 #include <linux/spi/spi_bitbang.h>
39 #include <asm/dcr-regs.h>
41 /* bits in mode register - bit 0 is MSb */
54 * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
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Dspi-loongson-core.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Loongson SPI Support
14 #include <linux/spi/spi.h>
16 #include "spi-loongson.h"
18 static inline void loongson_spi_write_reg(struct loongson_spi *spi, unsigned char reg, in loongson_spi_write_reg() argument
21 writeb(data, spi->base + reg); in loongson_spi_write_reg()
24 static inline char loongson_spi_read_reg(struct loongson_spi *spi, unsigned char reg) in loongson_spi_read_reg() argument
26 return readb(spi->base + reg); in loongson_spi_read_reg()
29 static void loongson_spi_set_cs(struct spi_device *spi, bool en) in loongson_spi_set_cs() argument
32 unsigned char mask = (BIT(4) | BIT(0)) << spi_get_chipselect(spi, 0); in loongson_spi_set_cs()
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Dspi-geni-qcom.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
6 #include <linux/dma-mapping.h>
7 #include <linux/dma/qcom-gpi-dma.h>
16 #include <linux/soc/qcom/geni-se.h>
17 #include <linux/spi/spi.h>
20 /* SPI SE specific registers and respective register fields */
59 /* M_CMD OP codes for SPI */
66 /* M_CMD params for SPI */
108 struct geni_se *se = &mas->se; in spi_slv_setup()
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Dspi-mpc52xx-psc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MPC52xx PSC in SPI mode driver.
20 #include <linux/spi/spi.h>
47 static int mpc52xx_psc_spi_transfer_setup(struct spi_device *spi, in mpc52xx_psc_spi_transfer_setup() argument
50 struct mpc52xx_psc_spi_cs *cs = spi->controller_state; in mpc52xx_psc_spi_transfer_setup()
52 cs->speed_hz = (t && t->speed_hz) in mpc52xx_psc_spi_transfer_setup()
53 ? t->speed_hz : spi->max_speed_hz; in mpc52xx_psc_spi_transfer_setup()
54 cs->bits_per_word = (t && t->bits_per_word) in mpc52xx_psc_spi_transfer_setup()
55 ? t->bits_per_word : spi->bits_per_word; in mpc52xx_psc_spi_transfer_setup()
56 cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8; in mpc52xx_psc_spi_transfer_setup()
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/linux-6.12.1/arch/mips/include/asm/octeon/
Dcvmx-spi.h7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 * This file contains defines for the SPI interface
35 #include <asm/octeon/cvmx-gmxx-defs.h>
37 /* CSR typedefs have been moved to cvmx-csr-*.h */
49 int (*reset_cb) (int interface, cvmx_spi_mode_t mode);
52 int (*calendar_setup_cb) (int interface, cvmx_spi_mode_t mode,
56 int (*clock_detect_cb) (int interface, cvmx_spi_mode_t mode,
60 int (*training_cb) (int interface, cvmx_spi_mode_t mode, int timeout);
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/linux-6.12.1/Documentation/devicetree/bindings/iio/adc/
Dadi,ad7944.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <Michael.Hennerich@analog.com>
11 - Nuno Sá <nuno.sa@analog.com>
14 A family of pin-compatible single channel differential analog to digital
15 converters with SPI support in a LFCSP package.
21 $ref: /schemas/spi/spi-peripheral-props.yaml#
26 - adi,ad7944
27 - adi,ad7985
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/linux-6.12.1/drivers/net/wan/
Dslic_ds26522.c1 // SPDX-License-Identifier: GPL-2.0-or-later
16 #include <linux/spi/spi.h>
38 static void slic_write(struct spi_device *spi, u16 addr, in slic_write() argument
49 /* write spi addr and value */ in slic_write()
50 spi_write(spi, &temp[0], SLIC_THREE_LEN); in slic_write()
53 static u8 slic_read(struct spi_device *spi, u16 addr) in slic_read() argument
62 spi_write_then_read(spi, &temp[0], SLIC_TWO_LEN, &data, in slic_read()
69 static bool get_slic_product_code(struct spi_device *spi) in get_slic_product_code() argument
73 device_id = slic_read(spi, DS26522_IDR_ADDR); in get_slic_product_code()
80 static void ds26522_e1_spec_config(struct spi_device *spi) in ds26522_e1_spec_config() argument
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/linux-6.12.1/drivers/staging/greybus/
Dspilib.c1 // SPDX-License-Identifier: GPL-2.0
3 * Greybus SPI library
5 * Copyright 2014-2016 Google Inc.
6 * Copyright 2014-2016 Linaro Ltd.
14 #include <linux/spi/spi.h>
28 u16 mode; member
41 #define GB_SPI_STATE_MSG_ERROR ((void *)-1)
45 static struct spi_controller *get_controller_from_spi(struct gb_spilib *spi) in get_controller_from_spi() argument
47 return gb_connection_get_data(spi->connection); in get_controller_from_spi()
54 data_max -= sizeof(struct gb_spi_transfer_request); in tx_header_fit_operation()
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/linux-6.12.1/drivers/media/dvb-frontends/cxd2880/
Dcxd2880_spi_device.c1 // SPDX-License-Identifier: GPL-2.0
4 * Sony CXD2880 DVB-T2/T tuner + demodulator driver
5 * SPI access functions
10 #include <linux/spi/spi.h>
14 static int cxd2880_spi_device_write(struct cxd2880_spi *spi, in cxd2880_spi_device_write() argument
22 if (!spi || !spi->user || !data || size == 0) in cxd2880_spi_device_write()
23 return -EINVAL; in cxd2880_spi_device_write()
25 spi_device = spi->user; in cxd2880_spi_device_write()
33 result = spi_sync(spi_device->spi, &msg); in cxd2880_spi_device_write()
36 return -EIO; in cxd2880_spi_device_write()
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/linux-6.12.1/include/trace/events/
Dspi.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 #define TRACE_SYSTEM spi
22 __entry->bus_num = controller->bus_num;
25 TP_printk("spi%d", (int)__entry->bus_num)
46 TP_PROTO(struct spi_device *spi, int status),
47 TP_ARGS(spi, status),
52 __field(unsigned long, mode)
59 __entry->bus_num = spi->controller->bus_num;
60 __entry->chip_select = spi_get_chipselect(spi, 0);
61 __entry->mode = spi->mode;
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/linux-6.12.1/Documentation/devicetree/bindings/net/
Dqca,qca7000.txt3 The QCA7000 is a serial-to-powerline bridge with a host interface which could
4 be configured either as SPI or UART slave. This configuration is done by
7 (a) Ethernet over SPI
9 In order to use the QCA7000 as SPI device it must be defined as a child of a
10 SPI master in the device tree.
13 - compatible : Should be "qca,qca7000"
14 - reg : Should specify the SPI chip select
15 - interrupts : The first cell should specify the index of the source
18 - spi-cpha : Must be set
19 - spi-cpol : Must be set
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/linux-6.12.1/arch/mips/cavium-octeon/executive/
Dcvmx-spi.c7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 * Support library for the SPI
34 #include <asm/octeon/cvmx-config.h>
36 #include <asm/octeon/cvmx-pko.h>
37 #include <asm/octeon/cvmx-spi.h>
39 #include <asm/octeon/cvmx-spxx-defs.h>
40 #include <asm/octeon/cvmx-stxx-defs.h>
41 #include <asm/octeon/cvmx-srxx-defs.h>
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/linux-6.12.1/Documentation/devicetree/bindings/spi/
Dspi-orion.txt1 Marvell Orion SPI device
4 - compatible : should be on of the following:
5 - "marvell,orion-spi" for the Orion, mv78x00, Kirkwood and Dove SoCs
6 - "marvell,armada-370-spi", for the Armada 370 SoCs
7 - "marvell,armada-375-spi", for the Armada 375 SoCs
8 - "marvell,armada-380-spi", for the Armada 38x SoCs
9 - "marvell,armada-390-spi", for the Armada 39x SoCs
10 - "marvell,armada-xp-spi", for the Armada XP SoCs
11 - reg : offset and length of the register set for the device.
13 the SPI direct access mode that some of the Marvell SoCs support
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/linux-6.12.1/drivers/hwmon/
Dmax31722.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * max31722 - hwmon driver for Maxim Integrated MAX31722/MAX31723 SPI
10 #include <linux/hwmon-sysfs.h>
13 #include <linux/spi/spi.h>
27 u8 mode; member
30 static int max31722_set_mode(struct max31722_data *data, u8 mode) in max31722_set_mode() argument
33 struct spi_device *spi = data->spi_device; in max31722_set_mode() local
36 (data->mode & MAX31722_MODE_MASK) | mode in max31722_set_mode()
39 ret = spi_write(spi, &buf, sizeof(buf)); in max31722_set_mode()
41 dev_err(&spi->dev, "failed to set sensor mode.\n"); in max31722_set_mode()
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/linux-6.12.1/drivers/tty/serial/
Dsc16is7xx_spi.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* SC16IS7xx SPI interface driver */
8 #include <linux/spi/spi.h>
14 /* SPI definitions */
17 static int sc16is7xx_spi_probe(struct spi_device *spi) in sc16is7xx_spi_probe() argument
25 /* Setup SPI bus */ in sc16is7xx_spi_probe()
26 spi->bits_per_word = 8; in sc16is7xx_spi_probe()
27 /* For all variants, only mode 0 is supported */ in sc16is7xx_spi_probe()
28 if ((spi->mode & SPI_MODE_X_MASK) != SPI_MODE_0) in sc16is7xx_spi_probe()
29 return dev_err_probe(&spi->dev, -EINVAL, "Unsupported SPI mode\n"); in sc16is7xx_spi_probe()
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/linux-6.12.1/Documentation/devicetree/bindings/iio/resolver/
Dadi,ad2s1210.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD2S1210 Resolver-to-Digital Converter
10 - Michael Hennerich <michael.hennerich@analog.com>
13 The AD2S1210 is a complete 10-bit to 16-bit resolution tracking
14 resolver-to-digital converter, integrating an on-board programmable
22 The mode of operation of the communication channel (parallel or serial) is
23 selected by the A0 and A1 input pins. In normal mode, data is latched by
24 toggling the SAMPLE line and can then be read directly. In configuration mode,
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/linux-6.12.1/Documentation/devicetree/bindings/mtd/
Dnxp-spifi.txt1 * NXP SPI Flash Interface (SPIFI)
3 NXP SPIFI is a specialized SPI interface for serial Flash devices.
4 It supports one Flash device with 1-, 2- and 4-bits width in SPI
5 mode 0 or 3. The controller operates in either command or memory
6 mode. In memory mode the Flash is accessible from the CPU as
10 - compatible : Should be "nxp,lpc1773-spifi"
11 - reg : the first contains the register location and length,
13 - reg-names: Should contain the reg names "spifi" and "flash"
14 - interrupts : Should contain the interrupt for the device
15 - clocks : The clocks needed by the SPIFI controller
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/linux-6.12.1/drivers/net/ethernet/wiznet/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
47 prompt "WIZnet interface mode"
52 bool "Direct address bus mode"
54 In direct address mode host system can directly access all registers
55 after mapping to Memory-Mapped I/O space.
58 bool "Indirect address bus mode"
60 In indirect address mode host system indirectly accesses registers
61 using Indirect Mode Address Register and Indirect Mode Data Register,
62 which are directly mapped to Memory-Mapped I/O space.
65 bool "Select interface mode in runtime"
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