Lines Matching +full:spi +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0-only
3 * SPI_PPC4XX SPI controller driver.
9 * Based in part on drivers/spi/spi_s3c24xx.c
17 * The PPC4xx SPI controller has no FIFO so each sent/received byte will
20 * during SPI transfers by setting max_speed_hz via the device tree.
35 #include <linux/spi/spi.h>
36 #include <linux/spi/spi_bitbang.h>
39 #include <asm/dcr-regs.h>
41 /* bits in mode register - bit 0 is MSb */
54 * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
55 * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
83 /* clock settings (SCP and CI) for various SPI modes */
92 u8 mode; member
103 * CDM = (OPBCLK/4*SCPClkOut) - 1
109 /* SPI Controller driver's private data. */
118 /* need this to set the SPI clock */
135 u8 mode; member
138 static int spi_ppc4xx_txrx(struct spi_device *spi, struct spi_transfer *t) in spi_ppc4xx_txrx() argument
143 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", in spi_ppc4xx_txrx()
144 t->tx_buf, t->rx_buf, t->len); in spi_ppc4xx_txrx()
146 hw = spi_controller_get_devdata(spi->controller); in spi_ppc4xx_txrx()
148 hw->tx = t->tx_buf; in spi_ppc4xx_txrx()
149 hw->rx = t->rx_buf; in spi_ppc4xx_txrx()
150 hw->len = t->len; in spi_ppc4xx_txrx()
151 hw->count = 0; in spi_ppc4xx_txrx()
154 data = hw->tx ? hw->tx[0] : 0; in spi_ppc4xx_txrx()
155 out_8(&hw->regs->txd, data); in spi_ppc4xx_txrx()
156 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR); in spi_ppc4xx_txrx()
157 wait_for_completion(&hw->done); in spi_ppc4xx_txrx()
159 return hw->count; in spi_ppc4xx_txrx()
162 static int spi_ppc4xx_setupxfer(struct spi_device *spi, struct spi_transfer *t) in spi_ppc4xx_setupxfer() argument
164 struct ppc4xx_spi *hw = spi_controller_get_devdata(spi->controller); in spi_ppc4xx_setupxfer()
165 struct spi_ppc4xx_cs *cs = spi->controller_state; in spi_ppc4xx_setupxfer()
171 speed = spi->max_speed_hz; in spi_ppc4xx_setupxfer()
178 if (t->speed_hz) in spi_ppc4xx_setupxfer()
179 speed = min(t->speed_hz, spi->max_speed_hz); in spi_ppc4xx_setupxfer()
182 if (!speed || (speed > spi->max_speed_hz)) { in spi_ppc4xx_setupxfer()
183 dev_err(&spi->dev, "invalid speed_hz (%d)\n", speed); in spi_ppc4xx_setupxfer()
184 return -EINVAL; in spi_ppc4xx_setupxfer()
188 out_8(&hw->regs->mode, cs->mode); in spi_ppc4xx_setupxfer()
192 scr = (hw->opb_freq / speed) - 1; in spi_ppc4xx_setupxfer()
196 dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed); in spi_ppc4xx_setupxfer()
198 if (in_8(&hw->regs->cdm) != cdm) in spi_ppc4xx_setupxfer()
199 out_8(&hw->regs->cdm, cdm); in spi_ppc4xx_setupxfer()
201 mutex_lock(&hw->bitbang.lock); in spi_ppc4xx_setupxfer()
202 if (!hw->bitbang.busy) { in spi_ppc4xx_setupxfer()
203 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE); in spi_ppc4xx_setupxfer()
206 mutex_unlock(&hw->bitbang.lock); in spi_ppc4xx_setupxfer()
211 static int spi_ppc4xx_setup(struct spi_device *spi) in spi_ppc4xx_setup() argument
213 struct spi_ppc4xx_cs *cs = spi->controller_state; in spi_ppc4xx_setup()
215 if (!spi->max_speed_hz) { in spi_ppc4xx_setup()
216 dev_err(&spi->dev, "invalid max_speed_hz (must be non-zero)\n"); in spi_ppc4xx_setup()
217 return -EINVAL; in spi_ppc4xx_setup()
223 return -ENOMEM; in spi_ppc4xx_setup()
224 spi->controller_state = cs; in spi_ppc4xx_setup()
229 * no need to read-modify-write in spi_ppc4xx_setup()
231 cs->mode = SPI_PPC4XX_MODE_SPE; in spi_ppc4xx_setup()
233 switch (spi->mode & SPI_MODE_X_MASK) { in spi_ppc4xx_setup()
235 cs->mode |= SPI_CLK_MODE0; in spi_ppc4xx_setup()
238 cs->mode |= SPI_CLK_MODE1; in spi_ppc4xx_setup()
241 cs->mode |= SPI_CLK_MODE2; in spi_ppc4xx_setup()
244 cs->mode |= SPI_CLK_MODE3; in spi_ppc4xx_setup()
248 if (spi->mode & SPI_LSB_FIRST) in spi_ppc4xx_setup()
249 cs->mode |= SPI_PPC4XX_MODE_RD; in spi_ppc4xx_setup()
263 status = in_8(&hw->regs->sr); in spi_ppc4xx_int()
268 * BSY de-asserts one cycle after the transfer is complete. The in spi_ppc4xx_int()
277 dev_dbg(hw->dev, "got interrupt but spi still busy?\n"); in spi_ppc4xx_int()
280 lstatus = in_8(&hw->regs->sr); in spi_ppc4xx_int()
284 dev_err(hw->dev, "busywait: too many loops!\n"); in spi_ppc4xx_int()
285 complete(&hw->done); in spi_ppc4xx_int()
289 status = in_8(&hw->regs->sr); in spi_ppc4xx_int()
290 dev_dbg(hw->dev, "loops %d status %x\n", cnt, status); in spi_ppc4xx_int()
294 count = hw->count; in spi_ppc4xx_int()
295 hw->count++; in spi_ppc4xx_int()
298 data = in_8(&hw->regs->rxd); in spi_ppc4xx_int()
299 if (hw->rx) in spi_ppc4xx_int()
300 hw->rx[count] = data; in spi_ppc4xx_int()
304 if (count < hw->len) { in spi_ppc4xx_int()
305 data = hw->tx ? hw->tx[count] : 0; in spi_ppc4xx_int()
306 out_8(&hw->regs->txd, data); in spi_ppc4xx_int()
307 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR); in spi_ppc4xx_int()
309 complete(&hw->done); in spi_ppc4xx_int()
315 static void spi_ppc4xx_cleanup(struct spi_device *spi) in spi_ppc4xx_cleanup() argument
317 kfree(spi->controller_state); in spi_ppc4xx_cleanup()
323 * On all 4xx PPC's the SPI bus is shared/multiplexed with in spi_ppc4xx_enable()
324 * the 2nd I2C bus. We need to enable the SPI bus before in spi_ppc4xx_enable()
341 struct device_node *np = op->dev.of_node; in spi_ppc4xx_of_probe()
342 struct device *dev = &op->dev; in spi_ppc4xx_of_probe()
349 return -ENOMEM; in spi_ppc4xx_of_probe()
350 host->dev.of_node = np; in spi_ppc4xx_of_probe()
353 hw->host = host; in spi_ppc4xx_of_probe()
354 hw->dev = dev; in spi_ppc4xx_of_probe()
356 init_completion(&hw->done); in spi_ppc4xx_of_probe()
359 bbp = &hw->bitbang; in spi_ppc4xx_of_probe()
360 bbp->ctlr = hw->host; in spi_ppc4xx_of_probe()
361 bbp->setup_transfer = spi_ppc4xx_setupxfer; in spi_ppc4xx_of_probe()
362 bbp->txrx_bufs = spi_ppc4xx_txrx; in spi_ppc4xx_of_probe()
363 bbp->use_dma = 0; in spi_ppc4xx_of_probe()
364 bbp->ctlr->setup = spi_ppc4xx_setup; in spi_ppc4xx_of_probe()
365 bbp->ctlr->cleanup = spi_ppc4xx_cleanup; in spi_ppc4xx_of_probe()
366 bbp->ctlr->bits_per_word_mask = SPI_BPW_MASK(8); in spi_ppc4xx_of_probe()
367 bbp->ctlr->use_gpio_descriptors = true; in spi_ppc4xx_of_probe()
369 * The SPI core will count the number of GPIO descriptors to figure in spi_ppc4xx_of_probe()
372 bbp->ctlr->num_chipselect = 0; in spi_ppc4xx_of_probe()
374 /* the spi->mode bits understood by this driver: */ in spi_ppc4xx_of_probe()
375 bbp->ctlr->mode_bits = in spi_ppc4xx_of_probe()
382 ret = -ENODEV; in spi_ppc4xx_of_probe()
386 clk = of_get_property(opbnp, "clock-frequency", NULL); in spi_ppc4xx_of_probe()
388 dev_err(dev, "OPB: no clock-frequency property set\n"); in spi_ppc4xx_of_probe()
390 ret = -ENODEV; in spi_ppc4xx_of_probe()
393 hw->opb_freq = *clk; in spi_ppc4xx_of_probe()
394 hw->opb_freq >>= 2; in spi_ppc4xx_of_probe()
402 hw->mapbase = resource.start; in spi_ppc4xx_of_probe()
403 hw->mapsize = resource_size(&resource); in spi_ppc4xx_of_probe()
406 if (hw->mapsize < sizeof(struct spi_ppc4xx_regs)) { in spi_ppc4xx_of_probe()
408 ret = -EINVAL; in spi_ppc4xx_of_probe()
416 hw->irqnum = ret; in spi_ppc4xx_of_probe()
418 ret = request_irq(hw->irqnum, spi_ppc4xx_int, in spi_ppc4xx_of_probe()
425 if (!request_mem_region(hw->mapbase, hw->mapsize, DRIVER_NAME)) { in spi_ppc4xx_of_probe()
427 ret = -EBUSY; in spi_ppc4xx_of_probe()
431 hw->regs = ioremap(hw->mapbase, sizeof(struct spi_ppc4xx_regs)); in spi_ppc4xx_of_probe()
433 if (!hw->regs) { in spi_ppc4xx_of_probe()
435 ret = -ENXIO; in spi_ppc4xx_of_probe()
441 /* Finally register our spi controller */ in spi_ppc4xx_of_probe()
442 dev->dma_mask = 0; in spi_ppc4xx_of_probe()
445 dev_err(dev, "failed to register SPI host\n"); in spi_ppc4xx_of_probe()
454 iounmap(hw->regs); in spi_ppc4xx_of_probe()
456 release_mem_region(hw->mapbase, hw->mapsize); in spi_ppc4xx_of_probe()
458 free_irq(hw->irqnum, hw); in spi_ppc4xx_of_probe()
471 spi_bitbang_stop(&hw->bitbang); in spi_ppc4xx_of_remove()
472 release_mem_region(hw->mapbase, hw->mapsize); in spi_ppc4xx_of_remove()
473 free_irq(hw->irqnum, hw); in spi_ppc4xx_of_remove()
474 iounmap(hw->regs); in spi_ppc4xx_of_remove()
479 { .compatible = "ibm,ppc4xx-spi", },
496 MODULE_DESCRIPTION("Simple PPC4xx SPI Driver");