1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * Freescale SPI controller driver.
10  * CPM SPI and QE buffer descriptors mode support:
19 #include <linux/dma-mapping.h>
33 #include <linux/spi/spi.h>
34 #include <linux/spi/spi_bitbang.h>
45 #include "spi-fsl-lib.h"
46 #include "spi-fsl-cpm.h"
47 #include "spi-fsl-spi.h"
66 		.compatible = "fsl,spi",
81 	if (dev->of_node) {  in fsl_spi_get_type()
82 		match = of_match_node(of_fsl_spi_match, dev->of_node);  in fsl_spi_get_type()
83 		if (match && match->data)  in fsl_spi_get_type()
84 			return ((struct fsl_spi_match_data *)match->data)->type;  in fsl_spi_get_type()
89 static void fsl_spi_change_mode(struct spi_device *spi)  in fsl_spi_change_mode()  argument
91 	struct mpc8xxx_spi *mspi = spi_controller_get_devdata(spi->controller);  in fsl_spi_change_mode()
92 	struct spi_mpc8xxx_cs *cs = spi->controller_state;  in fsl_spi_change_mode()
93 	struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;  in fsl_spi_change_mode()
94 	__be32 __iomem *mode = &reg_base->mode;  in fsl_spi_change_mode()  local
97 	if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))  in fsl_spi_change_mode()
100 	/* Turn off IRQs locally to minimize time that SPI is disabled. */  in fsl_spi_change_mode()
103 	/* Turn off SPI unit prior changing mode */  in fsl_spi_change_mode()
104 	mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);  in fsl_spi_change_mode()
106 	/* When in CPM mode, we need to reinit tx and rx. */  in fsl_spi_change_mode()
107 	if (mspi->flags & SPI_CPM_MODE) {  in fsl_spi_change_mode()
110 	mpc8xxx_spi_write_reg(mode, cs->hw_mode);  in fsl_spi_change_mode()
141 			*tx_shift = 32 - bits_per_word; /* MSB in bit 31 */  in fsl_spi_grlib_set_shifts()
143 			*rx_shift = 16 - bits_per_word; /* MSB in bit 15 */  in fsl_spi_grlib_set_shifts()
149 				       struct spi_device *spi,  in mspi_apply_cpu_mode_quirks()  argument
153 	cs->rx_shift = 0;  in mspi_apply_cpu_mode_quirks()
154 	cs->tx_shift = 0;  in mspi_apply_cpu_mode_quirks()
156 		cs->get_rx = mpc8xxx_spi_rx_buf_u8;  in mspi_apply_cpu_mode_quirks()
157 		cs->get_tx = mpc8xxx_spi_tx_buf_u8;  in mspi_apply_cpu_mode_quirks()
159 		cs->get_rx = mpc8xxx_spi_rx_buf_u16;  in mspi_apply_cpu_mode_quirks()
160 		cs->get_tx = mpc8xxx_spi_tx_buf_u16;  in mspi_apply_cpu_mode_quirks()
162 		cs->get_rx = mpc8xxx_spi_rx_buf_u32;  in mspi_apply_cpu_mode_quirks()
163 		cs->get_tx = mpc8xxx_spi_tx_buf_u32;  in mspi_apply_cpu_mode_quirks()
166 	if (mpc8xxx_spi->set_shifts)  in mspi_apply_cpu_mode_quirks()
167 		mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,  in mspi_apply_cpu_mode_quirks()
169 					!(spi->mode & SPI_LSB_FIRST));  in mspi_apply_cpu_mode_quirks()
171 	mpc8xxx_spi->rx_shift = cs->rx_shift;  in mspi_apply_cpu_mode_quirks()
172 	mpc8xxx_spi->tx_shift = cs->tx_shift;  in mspi_apply_cpu_mode_quirks()
173 	mpc8xxx_spi->get_rx = cs->get_rx;  in mspi_apply_cpu_mode_quirks()
174 	mpc8xxx_spi->get_tx = cs->get_tx;  in mspi_apply_cpu_mode_quirks()
177 static int fsl_spi_setup_transfer(struct spi_device *spi,  in fsl_spi_setup_transfer()  argument
184 	struct spi_mpc8xxx_cs	*cs = spi->controller_state;  in fsl_spi_setup_transfer()
186 	mpc8xxx_spi = spi_controller_get_devdata(spi->controller);  in fsl_spi_setup_transfer()
189 		bits_per_word = t->bits_per_word;  in fsl_spi_setup_transfer()
190 		hz = t->speed_hz;  in fsl_spi_setup_transfer()
193 	/* spi_transfer level calls that work per-word */  in fsl_spi_setup_transfer()
195 		bits_per_word = spi->bits_per_word;  in fsl_spi_setup_transfer()
198 		hz = spi->max_speed_hz;  in fsl_spi_setup_transfer()
200 	if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))  in fsl_spi_setup_transfer()
201 		mspi_apply_cpu_mode_quirks(cs, spi, mpc8xxx_spi, bits_per_word);  in fsl_spi_setup_transfer()
206 		bits_per_word = bits_per_word - 1;  in fsl_spi_setup_transfer()
209 	cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16  in fsl_spi_setup_transfer()
212 	cs->hw_mode |= SPMODE_LEN(bits_per_word);  in fsl_spi_setup_transfer()
214 	if ((mpc8xxx_spi->spibrg / hz) > 64) {  in fsl_spi_setup_transfer()
215 		cs->hw_mode |= SPMODE_DIV16;  in fsl_spi_setup_transfer()
216 		pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;  in fsl_spi_setup_transfer()
219 			  dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024);  in fsl_spi_setup_transfer()
223 		pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;  in fsl_spi_setup_transfer()
226 		pm--;  in fsl_spi_setup_transfer()
228 	cs->hw_mode |= SPMODE_PM(pm);  in fsl_spi_setup_transfer()
230 	fsl_spi_change_mode(spi);  in fsl_spi_setup_transfer()
238 	struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;  in fsl_spi_cpu_bufs()
240 	mspi->count = len;  in fsl_spi_cpu_bufs()
243 	mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);  in fsl_spi_cpu_bufs()
246 	word = mspi->get_tx(mspi);  in fsl_spi_cpu_bufs()
247 	mpc8xxx_spi_write_reg(&reg_base->transmit, word);  in fsl_spi_cpu_bufs()
252 static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t)  in fsl_spi_bufs()  argument
254 	struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(spi->controller);  in fsl_spi_bufs()
256 	unsigned int len = t->len;  in fsl_spi_bufs()
260 	reg_base = mpc8xxx_spi->reg_base;  in fsl_spi_bufs()
261 	bits_per_word = spi->bits_per_word;  in fsl_spi_bufs()
262 	if (t->bits_per_word)  in fsl_spi_bufs()
263 		bits_per_word = t->bits_per_word;  in fsl_spi_bufs()
270 	mpc8xxx_spi->tx = t->tx_buf;  in fsl_spi_bufs()
271 	mpc8xxx_spi->rx = t->rx_buf;  in fsl_spi_bufs()
273 	reinit_completion(&mpc8xxx_spi->done);  in fsl_spi_bufs()
275 	if (mpc8xxx_spi->flags & SPI_CPM_MODE)  in fsl_spi_bufs()
282 	wait_for_completion(&mpc8xxx_spi->done);  in fsl_spi_bufs()
285 	mpc8xxx_spi_write_reg(&reg_base->mask, 0);  in fsl_spi_bufs()
287 	if (mpc8xxx_spi->flags & SPI_CPM_MODE)  in fsl_spi_bufs()
290 	return mpc8xxx_spi->count;  in fsl_spi_bufs()
300 	first = list_first_entry(&m->transfers, struct spi_transfer,  in fsl_spi_prepare_message()
304 	 * In CPU mode, optimize large byte transfers to use larger  in fsl_spi_prepare_message()
307 	 * Some glitches can appear on the SPI clock when the mode changes.  in fsl_spi_prepare_message()
309 	 * now to change the mode without having a chip-select asserted.  in fsl_spi_prepare_message()
311 	list_for_each_entry(t, &m->transfers, transfer_list) {  in fsl_spi_prepare_message()
312 		if (t->speed_hz != first->speed_hz) {  in fsl_spi_prepare_message()
313 			dev_err(&m->spi->dev,  in fsl_spi_prepare_message()
315 			return -EINVAL;  in fsl_spi_prepare_message()
317 		if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {  in fsl_spi_prepare_message()
318 			if (t->len < 256 || t->bits_per_word != 8)  in fsl_spi_prepare_message()
320 			if ((t->len & 3) == 0)  in fsl_spi_prepare_message()
321 				t->bits_per_word = 32;  in fsl_spi_prepare_message()
322 			else if ((t->len & 1) == 0)  in fsl_spi_prepare_message()
323 				t->bits_per_word = 16;  in fsl_spi_prepare_message()
333 			if (m->spi->mode & SPI_LSB_FIRST && t->bits_per_word > 8)  in fsl_spi_prepare_message()
334 				return -EINVAL;  in fsl_spi_prepare_message()
335 			if (t->bits_per_word == 16 || t->bits_per_word == 32)  in fsl_spi_prepare_message()
336 				t->bits_per_word = 8; /* pretend its 8 bits */  in fsl_spi_prepare_message()
337 			if (t->bits_per_word == 8 && t->len >= 256 &&  in fsl_spi_prepare_message()
338 			    (mpc8xxx_spi->flags & SPI_CPM1))  in fsl_spi_prepare_message()
339 				t->bits_per_word = 16;  in fsl_spi_prepare_message()
342 	return fsl_spi_setup_transfer(m->spi, first);  in fsl_spi_prepare_message()
346 				struct spi_device *spi,  in fsl_spi_transfer_one()  argument
351 	status = fsl_spi_setup_transfer(spi, t);  in fsl_spi_transfer_one()
354 	if (t->len)  in fsl_spi_transfer_one()
355 		status = fsl_spi_bufs(spi, t);  in fsl_spi_transfer_one()
357 		return -EMSGSIZE;  in fsl_spi_transfer_one()
365 	return fsl_spi_setup_transfer(msg->spi, NULL);  in fsl_spi_unprepare_message()
368 static int fsl_spi_setup(struct spi_device *spi)  in fsl_spi_setup()  argument
375 	struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);  in fsl_spi_setup()
377 	if (!spi->max_speed_hz)  in fsl_spi_setup()
378 		return -EINVAL;  in fsl_spi_setup()
383 			return -ENOMEM;  in fsl_spi_setup()
384 		spi_set_ctldata(spi, cs);  in fsl_spi_setup()
387 	mpc8xxx_spi = spi_controller_get_devdata(spi->controller);  in fsl_spi_setup()
389 	reg_base = mpc8xxx_spi->reg_base;  in fsl_spi_setup()
391 	hw_mode = cs->hw_mode; /* Save original settings */  in fsl_spi_setup()
392 	cs->hw_mode = mpc8xxx_spi_read_reg(&reg_base->mode);  in fsl_spi_setup()
394 	cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH  in fsl_spi_setup()
397 	if (spi->mode & SPI_CPHA)  in fsl_spi_setup()
398 		cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;  in fsl_spi_setup()
399 	if (spi->mode & SPI_CPOL)  in fsl_spi_setup()
400 		cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;  in fsl_spi_setup()
401 	if (!(spi->mode & SPI_LSB_FIRST))  in fsl_spi_setup()
402 		cs->hw_mode |= SPMODE_REV;  in fsl_spi_setup()
403 	if (spi->mode & SPI_LOOP)  in fsl_spi_setup()
404 		cs->hw_mode |= SPMODE_LOOP;  in fsl_spi_setup()
406 	retval = fsl_spi_setup_transfer(spi, NULL);  in fsl_spi_setup()
408 		cs->hw_mode = hw_mode; /* Restore settings */  in fsl_spi_setup()
417 static void fsl_spi_cleanup(struct spi_device *spi)  in fsl_spi_cleanup()  argument
419 	struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);  in fsl_spi_cleanup()
422 	spi_set_ctldata(spi, NULL);  in fsl_spi_cleanup()
427 	struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;  in fsl_spi_cpu_irq()
431 		u32 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);  in fsl_spi_cpu_irq()
433 		if (mspi->rx)  in fsl_spi_cpu_irq()
434 			mspi->get_rx(rx_data, mspi);  in fsl_spi_cpu_irq()
440 			mpc8xxx_spi_read_reg(&reg_base->event)) &  in fsl_spi_cpu_irq()
445 	mpc8xxx_spi_write_reg(&reg_base->event, events);  in fsl_spi_cpu_irq()
447 	mspi->count -= 1;  in fsl_spi_cpu_irq()
448 	if (mspi->count) {  in fsl_spi_cpu_irq()
449 		u32 word = mspi->get_tx(mspi);  in fsl_spi_cpu_irq()
451 		mpc8xxx_spi_write_reg(&reg_base->transmit, word);  in fsl_spi_cpu_irq()
453 		complete(&mspi->done);  in fsl_spi_cpu_irq()
462 	struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;  in fsl_spi_irq()
465 	events = mpc8xxx_spi_read_reg(&reg_base->event);  in fsl_spi_irq()
469 	dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);  in fsl_spi_irq()
471 	if (mspi->flags & SPI_CPM_MODE)  in fsl_spi_irq()
479 static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)  in fsl_spi_grlib_cs_control()  argument
481 	struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(spi->controller);  in fsl_spi_grlib_cs_control()
482 	struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;  in fsl_spi_grlib_cs_control()
484 	u16 cs = spi_get_chipselect(spi, 0);  in fsl_spi_grlib_cs_control()
486 	if (cs < mpc8xxx_spi->native_chipselects) {  in fsl_spi_grlib_cs_control()
487 		slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel);  in fsl_spi_grlib_cs_control()
489 		mpc8xxx_spi_write_reg(&reg_base->slvsel, slvsel);  in fsl_spi_grlib_cs_control()
497 	struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;  in fsl_spi_grlib_probe()
501 	capabilities = mpc8xxx_spi_read_reg(&reg_base->cap);  in fsl_spi_grlib_probe()
503 	mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;  in fsl_spi_grlib_probe()
506 		mpc8xxx_spi->max_bits_per_word = mbits + 1;  in fsl_spi_grlib_probe()
508 	mpc8xxx_spi->native_chipselects = 0;  in fsl_spi_grlib_probe()
510 		mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);  in fsl_spi_grlib_probe()
511 		mpc8xxx_spi_write_reg(&reg_base->slvsel, 0xffffffff);  in fsl_spi_grlib_probe()
513 	host->num_chipselect = mpc8xxx_spi->native_chipselects;  in fsl_spi_grlib_probe()
514 	host->set_cs = fsl_spi_grlib_cs_control;  in fsl_spi_grlib_probe()
517 static void fsl_spi_cs_control(struct spi_device *spi, bool on)  in fsl_spi_cs_control()  argument
519 	struct device *dev = spi->dev.parent->parent;  in fsl_spi_cs_control()
523 	if (WARN_ON_ONCE(!pinfo->immr_spi_cs))  in fsl_spi_cs_control()
525 	iowrite32be(on ? 0 : SPI_BOOT_SEL_BIT, pinfo->immr_spi_cs);  in fsl_spi_cs_control()
540 		ret = -ENOMEM;  in fsl_spi_probe()
548 	host->setup = fsl_spi_setup;  in fsl_spi_probe()
549 	host->cleanup = fsl_spi_cleanup;  in fsl_spi_probe()
550 	host->prepare_message = fsl_spi_prepare_message;  in fsl_spi_probe()
551 	host->transfer_one = fsl_spi_transfer_one;  in fsl_spi_probe()
552 	host->unprepare_message = fsl_spi_unprepare_message;  in fsl_spi_probe()
553 	host->use_gpio_descriptors = true;  in fsl_spi_probe()
554 	host->set_cs = fsl_spi_cs_control;  in fsl_spi_probe()
557 	mpc8xxx_spi->max_bits_per_word = 32;  in fsl_spi_probe()
558 	mpc8xxx_spi->type = fsl_spi_get_type(dev);  in fsl_spi_probe()
564 	mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);  in fsl_spi_probe()
565 	if (IS_ERR(mpc8xxx_spi->reg_base)) {  in fsl_spi_probe()
566 		ret = PTR_ERR(mpc8xxx_spi->reg_base);  in fsl_spi_probe()
570 	if (mpc8xxx_spi->type == TYPE_GRLIB)  in fsl_spi_probe()
573 	if (mpc8xxx_spi->flags & SPI_CPM_MODE)  in fsl_spi_probe()
574 		host->bits_per_word_mask =  in fsl_spi_probe()
577 		host->bits_per_word_mask =  in fsl_spi_probe()
580 	host->bits_per_word_mask &=  in fsl_spi_probe()
581 		SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);  in fsl_spi_probe()
583 	if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)  in fsl_spi_probe()
584 		mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;  in fsl_spi_probe()
586 	if (mpc8xxx_spi->set_shifts)  in fsl_spi_probe()
588 		mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,  in fsl_spi_probe()
589 					&mpc8xxx_spi->tx_shift, 8, 1);  in fsl_spi_probe()
591 	/* Register for SPI Interrupt */  in fsl_spi_probe()
592 	ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq,  in fsl_spi_probe()
598 	reg_base = mpc8xxx_spi->reg_base;  in fsl_spi_probe()
600 	/* SPI controller initializations */  in fsl_spi_probe()
601 	mpc8xxx_spi_write_reg(&reg_base->mode, 0);  in fsl_spi_probe()
602 	mpc8xxx_spi_write_reg(&reg_base->mask, 0);  in fsl_spi_probe()
603 	mpc8xxx_spi_write_reg(&reg_base->command, 0);  in fsl_spi_probe()
604 	mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);  in fsl_spi_probe()
606 	/* Enable SPI interface */  in fsl_spi_probe()
607 	regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;  in fsl_spi_probe()
608 	if (mpc8xxx_spi->max_bits_per_word < 8) {  in fsl_spi_probe()
610 		regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);  in fsl_spi_probe()
612 	if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)  in fsl_spi_probe()
615 	mpc8xxx_spi_write_reg(&reg_base->mode, regval);  in fsl_spi_probe()
621 	dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,  in fsl_spi_probe()
622 		 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));  in fsl_spi_probe()
636 	struct device *dev = &ofdev->dev;  in of_fsl_spi_probe()
637 	struct device_node *np = ofdev->dev.of_node;  in of_fsl_spi_probe()
652 	type = fsl_spi_get_type(&ofdev->dev);  in of_fsl_spi_probe()
660 			pinfo->immr_spi_cs = ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET, 4);  in of_fsl_spi_probe()
661 			if (!pinfo->immr_spi_cs)  in of_fsl_spi_probe()
662 				return -ENOMEM;  in of_fsl_spi_probe()
676 			pdata->max_chipselect = 1;  in of_fsl_spi_probe()
678 			pdata->max_chipselect = ret + spisel_boot;  in of_fsl_spi_probe()
698 		iounmap(pinfo->immr_spi_cs);  in of_fsl_spi_probe()
723  * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
724  * only. The driver should go away soon, since newer MPC8323E-RDB's device
734 	if (!dev_get_platdata(&pdev->dev))  in plat_mpc8xxx_spi_probe()
735 		return -EINVAL;  in plat_mpc8xxx_spi_probe()
739 		return -EINVAL;  in plat_mpc8xxx_spi_probe()
745 	host = fsl_spi_probe(&pdev->dev, mem, irq);  in plat_mpc8xxx_spi_probe()
799 MODULE_DESCRIPTION("Simple Freescale SPI Driver");