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/linux-6.12.1/Documentation/devicetree/bindings/hwmon/
Dmax6697.txt4 - compatible:
16 - reg: I2C address
20 - smbus-timeout-disable
21 Set to disable SMBus timeout. If not specified, SMBus timeout will be
23 - extended-range-enable
26 - beta-compensation-enable
30 - alert-mask
34 - over-temperature-mask
35 Over-temperature bit mask. Over-temperature reporting disabled for
38 If not specified, over-temperature reporting will be enabled for all
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Dst,stts751.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Javier Carrasco <javier.carrasco.cruz@gmail.com>
19 smbus-timeout-disable:
21 When set, the smbus timeout function will be disabled.
25 - compatible
26 - reg
31 - |
33 #address-cells = <1>;
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Djedec,jc42.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Jedec JC-42.4 compatible temperature sensors
10 - Jean Delvare <jdelvare@suse.com>
11 - Guenter Roeck <linux@roeck-us.net>
16 const: jedec,jc-42.4-temp
19 - compatible
24 - const: jedec,jc-42.4-temp
25 - items:
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/linux-6.12.1/drivers/i2c/busses/
Di2c-amd8111.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SMBus 2.0 driver for AMD-8111 IO-Hub.
21 MODULE_DESCRIPTION("AMD8111 SMBus 2.0 driver");
61 #define AMD_EC_CMD_BD 0x83 /* disable burst mode */
68 static int amd_ec_wait_write(struct amd_smbus *smbus) in amd_ec_wait_write() argument
70 int timeout = 500; in amd_ec_wait_write() local
72 while ((inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_IBF) && --timeout) in amd_ec_wait_write()
75 if (!timeout) { in amd_ec_wait_write()
76 dev_warn(&smbus->dev->dev, in amd_ec_wait_write()
77 "Timeout while waiting for IBF to clear\n"); in amd_ec_wait_write()
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Di2c-nforce2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 SMBus driver for nVidia nForce2 MCP
7 Copyright (c) 2003 Hans-Frieder Vogt <hfvogt@arcor.de>,
9 SMBus 2.0 driver for AMD-8111 IO-Hub
21 nForce4 MCP-04 0034
35 /* Note: we assume there can only be one nForce2, with two SMBus interfaces */
50 MODULE_AUTHOR("Hans-Frieder Vogt <hfvogt@gmx.net>");
51 MODULE_DESCRIPTION("nForce2/3/4/5xx SMBus driver");
64 * nVidia nForce2 SMBus control register definitions
72 * ACPI 2.0 chapter 13 SMBus 2.0 EC register model
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Di2c-i801.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
16 * region SMBus Block proc. block
18 * ---------------------------------------------------------------------------
43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes
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Di2c-ali15x3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
34 ACPI-compliant Power Management Unit (PMU).
47 /* Note: we assume there can only be one ALI15X3, with one SMBus interface */
59 /* ALI15X3 SMBus address offsets */
127 - SMB I/O address is initialized in ali15x3_setup()
128 - Device is enabled in ali15x3_setup()
129 - We can use the addresses in ali15x3_setup()
133 The data sheet says that the address registers are read-only in ali15x3_setup()
143 /* Determine the address of the SMBus area */ in ali15x3_setup()
145 ali15x3_smba &= (0xffff & ~(ALI15X3_SMB_IOSIZE - 1)); in ali15x3_setup()
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Di2c-ali1535.c1 // SPDX-License-Identifier: GPL-2.0-or-later
18 the sequencing of the SMBus transactions has been modified
22 by comparing this driver to the i2c-ali15x3 driver.
26 ACPI-compliant Power Management Unit (PMU).
39 /* Note: we assume there can only be one ALI1535, with one SMBus interface */
52 /* ALI1535 SMBus address offsets */
87 #define ALI1535_DEV10B_EN 0x80 /* Enable 10-bit addressing in */
89 #define ALI1535_T_OUT 0x08 /* Time-out Command (write) */
90 #define ALI1535_A_HIGH_BIT9 0x08 /* Bit 9 of 10-bit address in */
91 /* Alert-Response-Address */
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Di2c-viapro.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
6 Copyright (C) 2005 - 2008 Jean Delvare <jdelvare@suse.de>
30 Note: we assume there can only be one device, with one SMBus interface.
50 /* SMBus address offsets */
62 /* SMBus data in configuration space can be found in two places,
84 MODULE_PARM_DESC(force, "Forcibly enable the SMBus. DANGEROUS!");
91 "Forcibly enable the SMBus at the given address. "
118 for (; i < I2C_SMBUS_BLOCK_MAX - 1; i++) in vt596_dump_regs()
127 /* Return -1 on error, 0 on success */
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Di2c-sis630.c1 // SPDX-License-Identifier: GPL-2.0-or-later
16 +------------------------+--------------------+-------------------+
18 +------------------------+--------------------+-------------------+
20 | SMBus registers offset | 0x80 | 0xE0 |
25 +------------------------+--------------------+-------------------+
28 Note: we assume there can only be one device, with one SMBus interface.
43 /* SIS630/730/964 SMBus registers */
58 #define MSTO_EN 0x40 /* Host Master Timeout Enable */
100 /* SMBus base address */
126 /* Make sure the SMBus host is ready to start transmitting. */ in sis630_transaction_start()
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Di2c-piix4.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
11 Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100
13 AMD Hudson-2, ML, CZ
18 SMBus interfaces.
32 #include <linux/i2c-smbus.h>
39 /* PIIX4 SMBus address offsets */
75 /* Multi-port constants */
89 * Hudson-2/Bolton port is always selected by bits 2:1 of register 0x2f.
129 DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"),
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Di2c-mlxbf.c1 // SPDX-License-Identifier: GPL-2.0
55 * Note that the following SMBus, CAUSE, GPIO and PLL register addresses
57 * memory-mapped region whose addresses are specified in either the DT or
62 * SMBus Master core clock frequency. Timing configurations are
63 * strongly dependent on the core clock frequency of the SMBus
67 /* Reference clock for Bluefield - 156 MHz. */
107 /* Transfer timeout occurred. */
146 * Note that Smbus GWs are on GPIOs 30:25. Two pins are used to control
149 * SMBUS GW0 -> bits[26:25]
150 * SMBUS GW1 -> bits[28:27]
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Di2c-stm32f7.c1 // SPDX-License-Identifier: GPL-2.0
14 * This driver is based on i2c-stm32f4.c
21 #include <linux/i2c-smbus.h>
38 #include "i2c-stm32.h"
186 * struct stm32f7_i2c_regs - i2c f7 registers backup
202 * struct stm32f7_i2c_spec - private i2c specification timing
224 * struct stm32f7_i2c_setup - private I2C timing setup parameters
244 * struct stm32f7_i2c_timings - private I2C output parameters
262 * struct stm32f7_i2c_msg - client specific data
263 * @addr: 8-bit or 10-bit slave addr, including r/w bit
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Di2c-bcm-iproc.c1 // SPDX-License-Identifier: GPL-2.0-only
138 #define M_RX_FIFO_MAX_THLD_VALUE (M_TX_RX_FIFO_SIZE - 1)
238 if (iproc_i2c->idm_base) { in iproc_i2c_rd_reg()
239 spin_lock_irqsave(&iproc_i2c->idm_lock, flags); in iproc_i2c_rd_reg()
240 writel(iproc_i2c->ape_addr_mask, in iproc_i2c_rd_reg()
241 iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET); in iproc_i2c_rd_reg()
242 val = readl(iproc_i2c->base + offset); in iproc_i2c_rd_reg()
243 spin_unlock_irqrestore(&iproc_i2c->idm_lock, flags); in iproc_i2c_rd_reg()
245 val = readl(iproc_i2c->base + offset); in iproc_i2c_rd_reg()
256 if (iproc_i2c->idm_base) { in iproc_i2c_wr_reg()
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Di2c-at91.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
18 #include <linux/dma-mapping.h>
23 #define AT91_I2C_TIMEOUT msecs_to_jiffies(100) /* transfer timeout */
33 #define AT91_TWI_MSDIS BIT(3) /* Master Transfer Disable */
35 #define AT91_TWI_SVDIS BIT(5) /* Slave Transfer Disable */
36 #define AT91_TWI_QUICK BIT(6) /* SMBus quick command */
40 #define AT91_TWI_ACMDIS BIT(17) /* Alternative Command Mode Disable */
45 #define AT91_TWI_FIFODIS BIT(29) /* FIFO Disable */
80 #define AT91_TWI_IDR 0x0028 /* Interrupt Disable Register */
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Di2c-nomadik.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2009 ST-Ericsson SA
11 * - The memory bus only supports 32-bit accesses.
12 * - A register must be configured for the I2C speed mode;
34 #define DRIVER_NAME "nmk-i2c"
73 #define I2C_MCR_A7 GENMASK(7, 1) /* 7-bit address */
74 #define I2C_MCR_EA10 GENMASK(10, 8) /* 10-bit Extended address */
87 /* Baud-rate counter register (BRCR) */
88 #define I2C_BRCR_BRCNT1 GENMASK(31, 16) /* Baud-rate counter 1 */
89 #define I2C_BRCR_BRCNT2 GENMASK(15, 0) /* Baud-rate counter 2 */
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/linux-6.12.1/Documentation/driver-api/
Dipmi.rst12 standardized database for field-replaceable units (FRUs) and a watchdog
25 -------------
32 No matter what, you must pick 'IPMI top-level message handler' to use
35 The message handler does not provide any user-level interfaces.
47 this, choose 'IPMI SMBus handler', but be ready to try to do some
50 these enabled and let the drivers auto-detect what is present.
61 "The SMBus Driver" on how to hand-configure your system.
65 the kernel, then via a kernel command-line option you can have the
71 'Disable watchdog shutdown on close'.
74 'IPMI Poweroff' to do this. The driver will auto-detect if the system
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/linux-6.12.1/drivers/input/mouse/
Dcyapa.c9 * Copyright (C) 2011-2015 Cypress Semiconductor, Inc.
10 * Copyright (C) 2011-2012 Google, Inc.
46 if (cyapa->gen == CYAPA_GEN6 && cyapa->state == CYAPA_STATE_GEN6_BL) in cyapa_is_pip_bl_mode()
49 if (cyapa->gen == CYAPA_GEN5 && cyapa->state == CYAPA_STATE_GEN5_BL) in cyapa_is_pip_bl_mode()
57 if (cyapa->gen == CYAPA_GEN6 && cyapa->state == CYAPA_STATE_GEN6_APP) in cyapa_is_pip_app_mode()
60 if (cyapa->gen == CYAPA_GEN5 && cyapa->state == CYAPA_STATE_GEN5_APP) in cyapa_is_pip_app_mode()
71 if (cyapa->gen == CYAPA_GEN3 && in cyapa_is_bootloader_mode()
72 cyapa->state >= CYAPA_STATE_BL_BUSY && in cyapa_is_bootloader_mode()
73 cyapa->state <= CYAPA_STATE_BL_ACTIVE) in cyapa_is_bootloader_mode()
84 if (cyapa->gen == CYAPA_GEN3 && cyapa->state == CYAPA_STATE_OP) in cyapa_is_operational_mode()
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/linux-6.12.1/drivers/net/ethernet/intel/e1000e/
Dich8lan.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
36 #define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */
93 /* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */
106 #define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */
107 #define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */
144 /* Half-duplex collision counts */
165 /* SMBus Control Phy Register */
176 #define I218_ULP_CONFIG1_RESET_TO_SMBUS 0x0100 /* Reset to SMBus mode */
179 /* disable clear of sticky ULP on PERST */
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Dich8lan.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
5 * 82562G-2 10/100 Network Connection
7 * 82562GT-2 10/100 Network Connection
9 * 82562V-2 10/100 Network Connection
10 * 82566DC-2 Gigabit Network Connection
12 * 82566DM-2 Gigabit Network Connection
19 * 82567LM-2 Gigabit Network Connection
20 * 82567LF-2 Gigabit Network Connection
21 * 82567V-2 Gigabit Network Connection
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/linux-6.12.1/drivers/usb/host/
Dpci-quirks.c1 // SPDX-License-Identifier: GPL-2.0
4 * Some of it includes work-arounds for PCI hardware and BIOS quirks.
5 * It may need to run early during booting -- before USB would normally
6 * initialize -- to ensure that Linux doesn't use any legacy modes.
22 #include "pci-quirks.h"
23 #include "xhci-ext-caps.h"
146 * amd_chipset_sb_type_init - initialize amd chipset southbridge type
148 * AMD FCH/SB generation and revision is identified by SMBus controller
156 pinfo->sb_type.gen = AMD_CHIPSET_UNKNOWN; in amd_chipset_sb_type_init()
158 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, in amd_chipset_sb_type_init()
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/linux-6.12.1/drivers/staging/olpc_dcon/
Dolpc_dcon.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright © 2006-2007 Red Hat, Inc.
6 * Copyright © 2006-2007 Advanced Micro Devices, Inc.
8 * Copyright (c) 2010-2011 Andres Salomon <dilinger@queued.net>
27 #include <linux/olpc-ec.h>
49 return i2c_smbus_write_word_data(dcon->client, reg, val); in dcon_write()
54 return i2c_smbus_read_word_data(dcon->client, reg); in dcon_read()
57 /* ===== API functions - these are called by a variety of users ==== */
67 rc = -ENXIO; in dcon_hw_init()
73 rc = pdata->init(dcon); in dcon_hw_init()
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/linux-6.12.1/drivers/hwmon/
Djc42.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * jc42.c - driver for Jedec JC42.4 compliant temperature sensors
69 /* SMBUS register */
70 #define SMBUS_STMOUT BIT(7) /* SMBus time-out, active low */
190 #define JC42_TEMP_MIN_EXTENDED (-40000)
219 mutex_lock(&data->update_lock); in jc42_read()
223 ret = regmap_read(data->regmap, JC42_REG_TEMP, &regval); in jc42_read()
230 ret = regmap_read(data->regmap, JC42_REG_TEMP_LOWER, &regval); in jc42_read()
237 ret = regmap_read(data->regmap, JC42_REG_TEMP_UPPER, &regval); in jc42_read()
244 ret = regmap_read(data->regmap, JC42_REG_TEMP_CRITICAL, in jc42_read()
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Dstts751.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2016-2017 Istituto Italiano di Tecnologia - RBCS - EDL
17 #include <linux/hwmon-sysfs.h>
32 0x48, 0x49, 0x38, 0x39, /* STTS751-0 */
33 0x4A, 0x4B, 0x3A, 0x3B, /* STTS751-1 */
104 * vice-vers. They are (mostly) taken from lm90 driver. Unit is in mC.
120 switch (priv->interval) { in stts751_adjust_resolution()
135 if (priv->res == res) in stts751_adjust_resolution()
138 priv->config &= ~STTS751_CONF_RES_MASK; in stts751_adjust_resolution()
139 priv->config |= res << STTS751_CONF_RES_SHIFT; in stts751_adjust_resolution()
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/linux-6.12.1/drivers/misc/eeprom/
Didt_89hpesx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
5 * IDT PCIe-switch NTB Linux driver
8 * Serge Semin <fancer.lancer@gmail.com>, <Sergey.Semin@t-platforms.ru>
11 * NOTE of the IDT 89HPESx SMBus-slave interface driver
13 * IDT PCIe-switches. IDT provides a simple SMBus interface to perform IO-
15 * SMBus of switches. Using that interface this the driver creates a simple
16 * binary sysfs-file in the device directory:
17 * /sys/bus/i2c/devices/<bus>-<devaddr>/eeprom
18 * In case if read-only flag is specified in the dts-node of device desription,
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