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/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dqcom,wcd937x-sdw.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,wcd937x-sdw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9370/WCD9375 Codec is a standalone Hi-Fi audio codec IC.
14 It has RX and TX Soundwire slave devices. This bindings is for the
24 qcom,tx-port-mapping:
26 Specifies static port mapping between device and host tx ports.
27 In the order of the device port index which are adc1_port, adc23_port,
[all …]
Dqcom,wcd939x-sdw.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,wcd939x-sdw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9390/WCD9395 Codec is a standalone Hi-Fi audio codec IC.
14 It has RX and TX Soundwire devices. This bindings is for the devices.
23 qcom,tx-port-mapping:
25 Specifies static port mapping between device and host tx ports.
26 In the order of the device port index.
[all …]
Dqcom,wcd938x-sdw.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,wcd938x-sdw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9380/WCD9385 Codec is a standalone Hi-Fi audio codec IC.
14 It has RX and TX Soundwire slave devices. This bindings is for the
24 qcom,tx-port-mapping:
26 Specifies static port mapping between slave and master tx ports.
27 In the order of slave port index.
[all …]
Dqcom,wcd939x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9390/WCD9395 Codec is a standalone Hi-Fi audio codec IC.
14 It has RX and TX Soundwire devices.
15 The WCD9390/WCD9395 IC has a functionally separate USB-C Mux subsystem
17 The Audio Headphone and Microphone data path between the Codec and the USB-C Mux
18 subsystems are external to the IC, thus requiring DT port-endpoint graph description
19 to handle USB-C altmode & orientation switching for Audio Accessory Mode.
[all …]
Drockchip,i2s-tdm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/rockchip,i2s-tdm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
18 - $ref: dai-common.yaml#
23 - rockchip,px30-i2s-tdm
24 - rockchip,rk1808-i2s-tdm
25 - rockchip,rk3308-i2s-tdm
26 - rockchip,rk3568-i2s-tdm
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Dqcom,wcd938x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9380/WCD9385 Codec is a standalone Hi-Fi audio codec IC.
14 It has RX and TX Soundwire slave devices.
17 - $ref: dai-common.yaml#
18 - $ref: qcom,wcd93xx-common.yaml#
23 - qcom,wcd9380-codec
24 - qcom,wcd9385-codec
[all …]
Dqcom,wcd937x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9370/WCD9375 Codec is a standalone Hi-Fi audio codec IC.
14 It has RX and TX Soundwire slave devices.
17 - $ref: dai-common.yaml#
18 - $ref: qcom,wcd93xx-common.yaml#
23 - const: qcom,wcd9370-codec
24 - items:
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/linux-6.12.1/drivers/net/ethernet/mellanox/mlx5/core/en/tc/
Dint_port.c1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
5 #include "en/mapping.h"
15 u32 mapping; member
28 struct mapping_ctx *metadata_mapping; /* Metadata for source port rewrite and matching */
34 MLX5_CAP_GEN(esw->dev, reg_c_preserve); in mlx5e_tc_int_port_supported()
39 return int_port->match_metadata; in mlx5e_tc_int_port_get_metadata()
46 * to int port or it came from the uplink, going in mlx5e_tc_int_port_get_flow_source()
47 * via internal port and hairpinned back to uplink in mlx5e_tc_int_port_get_flow_source()
48 * so we set the source to any port in this case. in mlx5e_tc_int_port_get_flow_source()
50 return int_port->type == MLX5E_TC_INT_PORT_EGRESS ? in mlx5e_tc_int_port_get_flow_source()
[all …]
/linux-6.12.1/drivers/net/ethernet/cortina/
Dgemini.c1 // SPDX-License-Identifier: GPL-2.0
11 * Michał Mirosław <mirq-linux@rere.qmqm.pl>
22 #include <linux/dma-mapping.h>
46 #define DRV_NAME "gmac-gemini"
49 static int debug = -1;
86 * struct gmac_queue_page - page buffer per-page info
88 * @mapping: the dma address handle
92 dma_addr_t mapping; member
156 spinlock_t irq_lock; /* Locks IRQ-related registers */
227 struct gemini_ethernet_port *port = netdev_priv(netdev); in gmac_update_config0_reg() local
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/linux-6.12.1/drivers/net/ethernet/ti/
Dcpsw_priv.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 dev_info(priv->dev, format, ## __VA_ARGS__); \
32 dev_err(priv->dev, format, ## __VA_ARGS__); \
38 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
44 dev_notice(priv->dev, format, ## __VA_ARGS__); \
127 #define CPSW_FIFO_SHAPERS_NUM (CPSW_TC_NUM - 1)
184 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
195 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
204 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
205 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
[all …]
/linux-6.12.1/drivers/soundwire/
Damd_manager.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
3 * Copyright (C) 2023-24 Advanced Micro Devices, Inc. All rights reserved.
208 * SDW0 Manager instance registers 6 CPU DAI (3 TX & 3 RX Ports)
209 * whereas SDW1 Manager Instance registers 2 CPU DAI (one TX & one RX port)
210 * Below is the CPU DAI <->Manager port number mapping
211 * i.e SDW0 Pin0 -> port number 0 -> AUDIO0 TX
212 * SDW0 Pin1 -> Port number 1 -> AUDIO1 TX
213 * SDW0 Pin2 -> Port number 2 -> AUDIO2 TX
214 * SDW0 Pin3 -> port number 3 -> AUDIO0 RX
215 * SDW0 Pin4 -> Port number 4 -> AUDIO1 RX
[all …]
/linux-6.12.1/drivers/net/ethernet/sunplus/
Dspl2sw_int.c1 // SPDX-License-Identifier: GPL-2.0
30 int port; in spl2sw_rx_poll() local
34 /* Process high-priority queue and then low-priority queue. */ in spl2sw_rx_poll()
36 rx_pos = comm->rx_pos[queue]; in spl2sw_rx_poll()
37 rx_count = comm->rx_desc_num[queue]; in spl2sw_rx_poll()
40 sinfo = comm->rx_skb_info[queue] + rx_pos; in spl2sw_rx_poll()
41 desc = comm->rx_desc[queue] + rx_pos; in spl2sw_rx_poll()
42 cmd = desc->cmd1; in spl2sw_rx_poll()
47 port = FIELD_GET(RXD_PKT_SP, cmd); in spl2sw_rx_poll()
48 if (port < MAX_NETDEV_NUM && comm->ndev[port]) in spl2sw_rx_poll()
[all …]
Dspl2sw_define.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define MAX_NETDEV_NUM 2 /* Maximum # of net-device */
17 #define MAC_INT_PORT_ST_CHG BIT(19) /* Port Status Change */
21 #define MAC_INT_TX_SOC_PAUSE_ON BIT(15) /* Soc Port TX Pause On */
22 #define MAC_INT_RX_SOC_QUE_FULL BIT(14) /* Soc Port Out Queue Full */
23 #define MAC_INT_TX_LAN1_QUE_FULL BIT(9) /* Port 1 Out Queue Full */
24 #define MAC_INT_TX_LAN0_QUE_FULL BIT(8) /* Port 0 Out Queue Full */
27 #define MAC_INT_RX_DONE_L BIT(5) /* RX Low Priority Done */
28 #define MAC_INT_RX_DONE_H BIT(4) /* RX High Priority Done */
32 #define MAC_INT_RX_DES_ERR BIT(0) /* Rx Descriptor Error */
[all …]
/linux-6.12.1/drivers/net/ethernet/mscc/
Docelot_fdma.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
24 regmap_write(ocelot->targets[FDMA], reg, data); in ocelot_fdma_writel()
31 regmap_read(ocelot->targets[FDMA], reg, &retval); in ocelot_fdma_readl()
43 return (dma - base) / sizeof(struct ocelot_fdma_dcb); in ocelot_fdma_dma_idx()
48 return unlikely(idx == ring_sz - 1) ? 0 : idx + 1; in ocelot_fdma_idx_next()
53 return unlikely(idx == 0) ? ring_sz - 1 : idx - 1; in ocelot_fdma_idx_prev()
58 struct ocelot_fdma_rx_ring *rx_ring = &fdma->rx_ring; in ocelot_fdma_rx_ring_free()
60 if (rx_ring->next_to_use >= rx_ring->next_to_clean) in ocelot_fdma_rx_ring_free()
61 return OCELOT_FDMA_RX_RING_SIZE - in ocelot_fdma_rx_ring_free()
62 (rx_ring->next_to_use - rx_ring->next_to_clean) - 1; in ocelot_fdma_rx_ring_free()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/hsi/
Domap-ssi.txt9 - compatible: Should include "ti,omap3-ssi" or "ti,omap4-hsi"
10 - reg-names: Contains the values "sys" and "gdd" (in this order).
11 - reg: Contains a matching register specifier for each entry
12 in reg-names.
13 - interrupt-names: Contains the value "gdd_mpu".
14 - interrupts: Contains matching interrupt information for each entry
15 in interrupt-names.
16 - ranges: Represents the bus address mapping between the main
18 - clock-names: Must include the following entries:
22 - clocks: Contains a matching clock specifier for each entry in
[all …]
/linux-6.12.1/drivers/net/ethernet/broadcom/
Dbcmsysport.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom BCM7xxx System Port Ethernet MAC driver
34 u32 reg = readl_relaxed(priv->base + offset + off); \
40 writel_relaxed(val, priv->base + offset + off); \
59 if (priv->is_lite && off >= RDMA_STATUS) in rdma_readl()
61 return readl_relaxed(priv->base + SYS_PORT_RDMA_OFFSET + off); in rdma_readl()
66 if (priv->is_lite && off >= RDMA_STATUS) in rdma_writel()
68 writel_relaxed(val, priv->base + SYS_PORT_RDMA_OFFSET + off); in rdma_writel()
73 if (!priv->is_lite) { in tdma_control_bit()
83 /* L2-interrupt masking/unmasking helpers, does automatic saving of the applied
[all …]
/linux-6.12.1/include/xen/interface/io/
Dnetif.h1 /* SPDX-License-Identifier: MIT */
5 * Unified network-device I/O interface for Xen guest OSes.
7 * Copyright (c) 2003-2004, Keir Fraser
37 * If the client sends notification for rx requests then it should specify
38 * feature 'feature-rx-notify' via xenbus. Otherwise the backend will assume
43 * "feature-split-event-channels" is introduced to separate guest TX
44 * and RX notification. Backend either doesn't support this feature or
48 * channels for TX and RX, advertise them to backend as
49 * "event-channel-tx" and "event-channel-rx" respectively. If frontend
50 * doesn't want to use this feature, it just writes "event-channel"
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/linux-6.12.1/Documentation/networking/
Dscaling.rst1 .. SPDX-License-Identifier: GPL-2.0
13 multi-processor systems.
17 - RSS: Receive Side Scaling
18 - RPS: Receive Packet Steering
19 - RFS: Receive Flow Steering
20 - Accelerated Receive Flow Steering
21 - XPS: Transmit Packet Steering
28 (multi-queue). On reception, a NIC can send different packets to different
33 generally known as “Receive-side Scaling” (RSS). The goal of RSS and
35 Multi-queue distribution can also be used for traffic prioritization, but
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/net/
Dibm,emac.txt8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
[all …]
Dcavium-pip.txt10 - compatible: "cavium,octeon-3860-pip"
14 - reg: The base address of the PIP's register bank.
16 - #address-cells: Must be <1>.
18 - #size-cells: Must be <0>.
21 - compatible: "cavium,octeon-3860-pip-interface"
25 - reg: The interface number.
27 - #address-cells: Must be <1>.
29 - #size-cells: Must be <0>.
31 Properties for PIP port which is a child the PIP interface:
32 - compatible: "cavium,octeon-3860-pip-port"
[all …]
/linux-6.12.1/drivers/tty/serial/8250/
D8250_dma.c1 // SPDX-License-Identifier: GPL-2.0+
3 * 8250_dma.c - DMA Engine API support for 8250.c
10 #include <linux/dma-mapping.h>
17 struct uart_8250_dma *dma = p->dma; in __dma_tx_complete()
18 struct tty_port *tport = &p->port.state->port; in __dma_tx_complete()
22 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, in __dma_tx_complete()
25 uart_port_lock_irqsave(&p->port, &flags); in __dma_tx_complete()
27 dma->tx_running = 0; in __dma_tx_complete()
29 uart_xmit_advance(&p->port, dma->tx_size); in __dma_tx_complete()
31 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in __dma_tx_complete()
[all …]
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dsm8650-qrd.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/leds/common.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
22 compatible = "qcom,sm8650-qrd", "qcom,sm8650";
30 stdout-path = "serial0:115200n8";
33 gpio-keys {
34 compatible = "gpio-keys";
36 pinctrl-0 = <&volume_up_n>;
37 pinctrl-names = "default";
[all …]
/linux-6.12.1/tools/testing/selftests/net/
Dtoeplitz.sh2 # SPDX-License-Identifier: GPL-2.0
4 # extended toeplitz test: test rxhash plus, optionally, either (1) rss mapping
5 # from rxhash to rx queue ('-rss') or (2) rps mapping from rxhash to cpu
6 # ('-rps <rps_map>')
8 # irq-pattern-prefix can be derived from /sys/kernel/irq/*/action,
9 # which is a driver-specific encoding.
11 # invoke as ./toeplitz.sh (-i <iface>) -u|-t -4|-6 \
12 # [(-rss -irq_prefix <irq-pattern-prefix>)|(-rps <rps_map>)]
23 PORT=8000
34 echo $(ethtool -x "${DEV}" |
[all …]
/linux-6.12.1/drivers/net/ethernet/microchip/sparx5/
Dsparx5_fdma.c1 // SPDX-License-Identifier: GPL-2.0+
7 * https://github.com/microchip-ung/sparx-5_reginfo
15 #include <linux/dma-mapping.h>
30 *dataptr = fdma->dma + (sizeof(struct fdma_dcb) * fdma->n_dcbs) + in sparx5_fdma_tx_dataptr_cb()
31 ((dcb * fdma->n_dbs + db) * fdma->db_size); in sparx5_fdma_tx_dataptr_cb()
39 struct sparx5 *sparx5 = fdma->priv; in sparx5_fdma_rx_dataptr_cb()
40 struct sparx5_rx *rx = &sparx5->rx; in sparx5_fdma_rx_dataptr_cb() local
43 skb = __netdev_alloc_skb(rx->ndev, fdma->db_size, GFP_ATOMIC); in sparx5_fdma_rx_dataptr_cb()
45 return -ENOMEM; in sparx5_fdma_rx_dataptr_cb()
47 *dataptr = virt_to_phys(skb->data); in sparx5_fdma_rx_dataptr_cb()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/iommu/
Dmediatek,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yong Wu <yong.wu@mediatek.com>
15 pagetable, and only supports 4K size page mapping. Generation two uses the
16 ARM Short-Descriptor translation table format for address translation.
24 +--------+
26 gals0-rx gals1-rx (Global Async Local Sync rx)
29 gals0-tx gals1-tx (Global Async Local Sync tx)
31 +--------+
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