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/linux-6.12.1/drivers/phy/motorola/
Dphy-mapphone-mdm6600.c1 // SPDX-License-Identifier: GPL-2.0
3 * Motorola Mapphone MDM6600 modem GPIO controlled USB PHY driver
18 #include <linux/phy/phy.h>
21 #define PHY_MDM6600_PHY_DELAY_MS 4000 /* PHY enable 2.2s to 3.5s */
23 #define PHY_MDM6600_WAKE_KICK_MS 600 /* time on after GPIO toggle */
28 PHY_MDM6600_ENABLE, /* USB PHY enable */
30 PHY_MDM6600_RESET, /* Device reset */
35 PHY_MDM6600_MODE0, /* out USB mode0 and OOB wake */
36 PHY_MDM6600_MODE1, /* out USB mode1, in OOB wake */
55 * MDM6600 command codes. These are based on Motorola Mapphone Linux
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/net/
Dsmsc,lan9115.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller
10 - Shawn Guo <shawnguo@kernel.org>
13 - $ref: ethernet-controller.yaml#
18 - const: smsc,lan9115
19 - items:
20 - enum:
21 - smsc,lan89218
[all …]
/linux-6.12.1/arch/arm64/boot/dts/rockchip/
Drk3308-rock-pi-s.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/leds/common.h>
24 stdout-path = "serial0:1500000n8";
28 compatible = "gpio-leds";
29 pinctrl-names = "default";
30 pinctrl-0 = <&green_led>, <&heartbeat_led>;
32 green-led {
34 default-state = "on";
38 linux,default-trigger = "default-on";
[all …]
Drk3308-rock-s0.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/leds/common.h>
10 compatible = "radxa,rock-s0", "rockchip,rk3308";
20 stdout-path = "serial0:1500000n8";
24 compatible = "gpio-leds";
25 pinctrl-names = "default";
26 pinctrl-0 = <&pwr_led>;
28 led-green {
30 default-state = "on";
[all …]
Drk3566-box-demo.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Based on Quartz64 DT by: Peter Geis pgwipeout@gmail.com
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/pinctrl/rockchip.h>
13 #include <dt-bindings/soc/rockchip,vop2.h>
18 compatible = "rockchip,rk3566-box-demo", "rockchip,rk3566";
28 stdout-path = "serial2:1500000n8";
31 gmac1_clkin: external-gmac1-clock {
[all …]
Drk3566-orangepi-3b-v2.1.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include "rk3566-orangepi-3b.dtsi"
9 compatible = "xunlong,orangepi-3b-v2.1", "xunlong,orangepi-3b", "rockchip,rk3566";
11 vccio_phy1: regulator-1v8-vccio-phy {
12 compatible = "regulator-fixed";
13 regulator-name = "vccio_phy1";
14 regulator-always-on;
15 regulator-boot-on;
16 regulator-max-microvolt = <1800000>;
[all …]
Drk3328-a1.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
2 // Copyright (c) 2017-2019 Arm Ltd.
4 /dts-v1/;
9 compatible = "azw,beelink-a1", "rockchip,rk3328";
21 * /-------
22 * L / o <- Gnd
23 * e / o <-- Rx
24 * f / o <--- Tx
25 * t / o <---- +3.3v
29 stdout-path = "serial2:1500000n8";
[all …]
Drk3368-lba3368.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/clock/rockchip,rk808.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/sound/rt5640.h>
25 stdout-path = "serial1:115200n8";
33 adc-key {
34 compatible = "adc-keys";
35 io-channels = <&saradc 1>;
[all …]
Drk3568-rock-3b.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/soc/rockchip,vop2.h>
13 compatible = "radxa,rock-3b", "rockchip,rk3568";
24 stdout-path = "serial2:1500000n8";
27 hdmi-con {
28 compatible = "hdmi-connector";
[all …]
Drk3568-wolfvision-pf5-io-expander.dtso1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
8 /dts-v1/;
11 #include <dt-bindings/clock/rk3568-cru.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/pinctrl/rockchip.h>
17 gmac0_clkin: external-gmac0-clock {
18 compatible = "fixed-clock";
19 clock-frequency = <50000000>;
20 clock-output-names = "gmac0_clkin";
[all …]
/linux-6.12.1/drivers/char/tpm/
Dtpm_tis_spi_cr50.c1 // SPDX-License-Identifier: GPL-2.0
7 * It is based on tpm_tis_spi driver by Peter Huewe and Christophe Ricard.
23 * - can go to sleep not earlier than after CR50_SLEEP_DELAY_MSEC.
24 * - needs up to CR50_WAKE_START_DELAY_USEC to wake after sleep.
25 * - requires waiting for "ready" IRQ, if supported; or waiting for at least
27 * - waits for up to CR50_FLOW_CONTROL for flow control 'ready' indication.
55 static inline struct cr50_spi_phy *to_cr50_spi_phy(struct tpm_tis_spi_phy *phy) in to_cr50_spi_phy() argument
57 return container_of(phy, struct cr50_spi_phy, spi_phy); in to_cr50_spi_phy()
69 cr50_phy->irq_confirmed = true; in cr50_spi_irq_handler()
70 complete(&cr50_phy->spi_phy.ready); in cr50_spi_irq_handler()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/usb/
Ddwc2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
13 - $ref: usb-drd.yaml#
14 - $ref: usb-hcd.yaml#
19 - const: brcm,bcm2835-usb
20 - const: hisilicon,hi6220-usb
21 - const: ingenic,jz4775-otg
22 - const: ingenic,jz4780-otg
[all …]
Dam33xx-usb.txt3 - compatible: ti,am33xx-usb
4 - reg: offset and length of the usbss register sets
5 - ti,hwmods : must be "usb_otg_hs"
8 at least a control module node, USB node and a PHY node. The second USB
9 node and its PHY node are optional. The DMA node is also optional.
11 Reset module
13 - compatible: ti,am335x-usb-ctrl-module
14 - reg: offset and length of the "USB control registers" in the "Control
15 Module" block. A second offset and length for the USB wake up control
17 - reg-names: "phy_ctrl" for the "USB control registers" and "wakeup" for
[all …]
/linux-6.12.1/arch/arm/boot/dts/rockchip/
Drv1126-sonoff-ihost.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
16 stdout-path = "serial2:1500000n8";
19 vcc5v0_sys: regulator-vcc5v0-sys {
20 compatible = "regulator-fixed";
21 regulator-name = "vcc5v0_sys";
22 regulator-always-on;
23 regulator-boot-on;
24 regulator-min-microvolt = <5000000>;
25 regulator-max-microvolt = <5000000>;
28 sdio_pwrseq: pwrseq-sdio {
[all …]
Drk3288-veyron-fievel.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
9 #include "rk3288-veyron.dtsi"
10 #include "rk3288-veyron-analog-audio.dtsi"
14 compatible = "google,veyron-fievel-rev8", "google,veyron-fievel-rev7",
15 "google,veyron-fievel-rev6", "google,veyron-fievel-rev5",
16 "google,veyron-fievel-rev4", "google,veyron-fievel-rev3",
17 "google,veyron-fievel-rev2", "google,veyron-fievel-rev1",
18 "google,veyron-fievel-rev0", "google,veyron-fievel",
22 compatible = "regulator-fixed";
[all …]
/linux-6.12.1/drivers/net/usb/
Dsmsc95xx.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2007-2008 SMSC
38 /* SCSRs - System Control and Status Registers */
52 #define INT_STS_MAC_RTO_ (0x00040000) /* MAC Reset Time Out */
55 #define INT_STS_PHY_INT_ (0x00008000) /* PHY Interrupt */
83 #define HW_CFG_LRST_ (0x00000008) /* Soft Lite Reset */
84 #define HW_CFG_PSEL_ (0x00000004) /* External PHY Select */
86 #define HW_CFG_SRST_ (0x00000001) /* Soft Reset */
106 #define PM_CTL_PHY_RST_ (0x00000010) /* PHY Reset */
107 #define PM_CTL_WOL_EN_ (0x00000008) /* Wake On Lan Enable */
[all …]
/linux-6.12.1/drivers/net/ethernet/broadcom/genet/
Dbcmgenet_wol.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom GENET (Gigabit Ethernet) Wake-on-LAN support
5 * Copyright (c) 2014-2024 Broadcom
33 #include <linux/phy.h>
37 /* ethtool function - get WOL (Wake on LAN) settings, Only Magic Packet
43 struct device *kdev = &priv->pdev->dev; in bcmgenet_get_wol()
45 if (dev->phydev) in bcmgenet_get_wol()
46 phy_ethtool_get_wol(dev->phydev, wol); in bcmgenet_get_wol()
48 /* MAC is not wake-up capable, return what the PHY does */ in bcmgenet_get_wol()
52 /* Overlay MAC capabilities with that of the PHY queried before */ in bcmgenet_get_wol()
[all …]
/linux-6.12.1/drivers/usb/dwc2/
Dplatform.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * platform.c - DesignWare HS OTG Controller platform driver
13 #include <linux/dma-mapping.h>
17 #include <linux/phy/phy.h>
18 #include <linux/platform_data/s3c-hsotg.h>
19 #include <linux/reset.h>
39 * ------------------------------
41 * HST DEV any : ---
44 * DEV HST any : ---
56 hsotg->dr_mode = usb_get_dr_mode(hsotg->dev); in dwc2_get_dr_mode()
[all …]
/linux-6.12.1/drivers/net/phy/
Dbroadcom.c1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/net/phy/broadcom.c
8 * Broadcom BCM54810, BCM54811 BroadR-Reach transceivers.
15 #include "bcm-phy-lib.h"
18 #include <linux/phy.h>
27 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
30 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
32 MODULE_DESCRIPTION("Broadcom PHY driver");
44 /* Link modes for BCM58411 PHY */
57 /* Long-Distance Signaling (BroadR-Reach mode aneg) relevant linkmode bits */
[all …]
/linux-6.12.1/drivers/pci/controller/dwc/
Dpcie-qcom-ep.c1 // SPDX-License-Identifier: GPL-2.0
18 #include <linux/phy/pcie.h>
19 #include <linux/phy/phy.h>
23 #include <linux/reset.h>
27 #include "pcie-designware.h"
28 #include "pcie-qcom-common.h"
153 #define to_pcie_ep(x) dev_get_drvdata((x)->dev)
163 * struct qcom_pcie_ep_cfg - Per SoC config struct
164 * @hdma_support: HDMA support on this SoC
175 * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller
[all …]
/linux-6.12.1/drivers/net/ethernet/oki-semi/pch_gbe/
Dpch_gbe.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 1999 - 2010 Intel Corporation.
26 * pch_gbe_regs_mac_adr - Structure holding values of mac address registers
35 * pch_udc_regs - Structure holding values of MAC registers
41 u32 RESET; member
105 #define PCH_GBE_INT_PHY_INT 0x00100000 /* Interruption from PHY */
106 #define PCH_GBE_INT_WOL_DET 0x01000000 /* Wake On LAN Event detection. */
116 /* Reset */
117 #define PCH_GBE_ALL_RST 0x80000000 /* All reset */
118 #define PCH_GBE_TX_RST 0x00008000 /* TX MAC, TX FIFO, TX DMA reset */
[all …]
/linux-6.12.1/drivers/net/ethernet/intel/igb/
De1000_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
12 /* Wake Up Control */
15 /* Wake Up Filter Control */
22 /* Wake Up Status */
29 /* Packet types that are enabled for wake packet delivery */
37 /* Wake Up Packet Length */
40 /* Wake Up Packet Memory stores the first 128 bytes of the wake up packet */
49 /* Physical Func Reset Done Indication */
62 /* Interrupt acknowledge Auto-mask */
[all …]
/linux-6.12.1/drivers/net/ethernet/intel/igc/
Digc_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
18 /* Wake Up Control */
21 /* Wake Up Filter Control */
41 /* Wake Up Status */
48 /* Packet types that are enabled for wake packet delivery */
56 /* Wake Up Packet Length */
59 /* Wake Up Packet Memory stores the first 128 bytes of the wake up packet */
90 /* Loop limit on how long we wait for auto-negotiation to complete */
132 #define IGC_CTRL_RST 0x04000000 /* Global reset */
134 #define IGC_CTRL_PHY_RST 0x80000000 /* PHY Reset */
[all …]
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dsa8295p-adp.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
11 #include <dt-bindings/spmi/spmi.h>
12 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
15 #include "sa8540p-pmics.dtsi"
19 compatible = "qcom,sa8295p-adp", "qcom,sa8540p";
26 stdout-path = "serial0:115200n8";
29 dp2-connector {
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/pci/
Dqcom,pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
20 - enum:
21 - qcom,pcie-apq8064
22 - qcom,pcie-apq8084
23 - qcom,pcie-ipq4019
[all …]

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