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/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dfsl,imx8-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Richard Zhu <hongxing.zhu@nxp.com>
13 "#phy-cells":
18 - fsl,imx8mm-pcie-phy
19 - fsl,imx8mp-pcie-phy
27 clock-names:
29 - const: ref
[all …]
Dfsl,imx8qm-hsio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-hsio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Richard Zhu <hongxing.zhu@nxp.com>
15 - fsl,imx8qm-hsio
16 - fsl,imx8qxp-hsio
19 - description: Base address and length of the PHY block
20 - description: HSIO control and status registers(CSR) of the PHY
21 - description: HSIO CSR of the controller bound to the PHY
[all …]
/linux-6.12.1/drivers/media/i2c/
Dtc358746.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TC358746 - Parallel <-> CSI-2 Bridge
8 * - Currently only 'Parallel-in -> CSI-out' mode is supported!
13 #include <linux/clk-provider.h>
19 #include <linux/phy/phy-mipi-dphy.h>
24 #include <media/v4l2-ctrls.h>
25 #include <media/v4l2-device.h>
26 #include <media/v4l2-fwnode.h>
27 #include <media/v4l2-mc.h>
29 /* 16-bit registers */
[all …]
Dtc358743.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * tc358743 - Toshiba HDMI to CSI-2 bridge
11 * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
12 * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
27 #include <linux/v4l2-dv-timings.h>
30 #include <media/v4l2-dv-timings.h>
31 #include <media/v4l2-device.h>
32 #include <media/v4l2-ctrls.h>
33 #include <media/v4l2-event.h>
34 #include <media/v4l2-fwnode.h>
[all …]
Dds90ub960.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the Texas Instruments DS90UB960-Q1 video deserializer
12 * - PM for serializer and remote peripherals. We need to manage:
13 * - VPOC
14 * - Power domain? Regulator? Somehow any remote device should be able to
16 * - Link between the deserializer and the serializer
17 * - Related to VPOC management. We probably always want to turn on the VPOC
19 * - Serializer's services: i2c, gpios, power
20 * - The serializer needs to resume before the remote peripherals can
22 * - How to handle gpios? Reserving a gpio essentially keeps the provider
[all …]
/linux-6.12.1/drivers/phy/freescale/
Dphy-fsl-imx8m-pcie.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
20 #include <dt-bindings/phy/phy-imx8-pcie.h>
79 pad_mode = imx8_phy->refclk_pad_mode; in imx8_pcie_phy_power_on()
80 switch (imx8_phy->drvdata->variant) { in imx8_pcie_phy_power_on()
82 reset_control_assert(imx8_phy->reset); in imx8_pcie_phy_power_on()
84 /* Tune PHY de-emphasis setting to pass PCIe compliance. */ in imx8_pcie_phy_power_on()
85 if (imx8_phy->tx_deemph_gen1) in imx8_pcie_phy_power_on()
86 writel(imx8_phy->tx_deemph_gen1, in imx8_pcie_phy_power_on()
87 imx8_phy->base + PCIE_PHY_TRSV_REG5); in imx8_pcie_phy_power_on()
[all …]
Dphy-fsl-imx8qm-hsio.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <dt-bindings/phy/phy.h>
20 #include <dt-bindings/phy/phy-imx8-pcie.h>
120 struct imx_hsio_priv *priv = lane->priv; in imx_hsio_init()
121 struct device *dev = priv->dev; in imx_hsio_init()
124 switch (lane->phy_type) { in imx_hsio_init()
126 lane->phy_mode = PHY_MODE_PCIE; in imx_hsio_init()
127 if (lane->ctrl_index == 0) { /* PCIEA */ in imx_hsio_init()
128 lane->ctrl_off = 0; in imx_hsio_init()
129 lane->phy_off = 0; in imx_hsio_init()
[all …]
/linux-6.12.1/drivers/pci/controller/cadence/
Dpci-j721e.c1 // SPDX-License-Identifier: GPL-2.0
3 * pci-j721e - PCIe controller driver for TI's J721E SoCs
5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
10 #include <linux/clk-provider.h>
25 #include "pcie-cadence.h"
56 struct clk *refclk; member
57 u32 mode; member
72 enum j721e_pcie_mode mode; member
83 return readl(pcie->user_cfg_base + offset); in j721e_pcie_user_readl()
89 writel(value, pcie->user_cfg_base + offset); in j721e_pcie_user_writel()
[all …]
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dimx8mm-iot-gateway.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 #include "imx8mm-ucm-som.dtsi"
6 #include <dt-bindings/phy/phy-imx8-pcie.h>
9 compatible = "compulab,imx8mm-iot-gateway", "compulab,imx8mm-ucm-som", "fsl,imx8mm";
11 regulator-usbhub-ena {
12 compatible = "regulator-fixed";
13 regulator-name = "usbhub_ena";
14 regulator-min-microvolt = <3300000>;
15 regulator-max-microvolt = <3300000>;
17 enable-active-high;
[all …]
Dimx8mm-venice-gw71xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
16 led-controller {
17 compatible = "gpio-leds";
18 pinctrl-names = "default";
19 pinctrl-0 = <&pinctrl_gpio_leds>;
21 led-0 {
25 default-state = "on";
[all …]
Dimx8mp-venice-gw75xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
11 led-controller {
12 compatible = "gpio-leds";
13 pinctrl-names = "default";
14 pinctrl-0 = <&pinctrl_gpio_leds>;
16 led-0 {
20 default-state = "on";
[all …]
Dimx8mp-venice-gw71xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
12 compatible = "gpio-usb-b-connector", "usb-b-connector";
13 pinctrl-names = "default";
14 pinctrl-0 = <&pinctrl_usbcon1>;
16 label = "Type-C";
17 id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
21 remote-endpoint = <&usb3_dwc>;
[all …]
Dimx8mm-beacon-baseboard.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 dmic_codec: dmic-codec {
11 compatible = "dmic-codec";
12 num-channels = <1>;
13 #sound-dai-cells = <0>;
17 compatible = "gpio-leds";
22 default-state = "off";
28 default-state = "off";
34 default-state = "off";
[all …]
Dimx8mm-venice-gw72xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
17 led-controller {
18 compatible = "gpio-leds";
19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_gpio_leds>;
22 led-0 {
26 default-state = "on";
[all …]
Dimx8mm-venice-gw73xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
17 led-controller {
18 compatible = "gpio-leds";
19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_gpio_leds>;
22 led-0 {
26 default-state = "on";
[all …]
Dimx8mp-dhcom-pdk2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 * DHCM-iMX8ML8-C160-R409-F1638-SPI16-GE-CAN2-SD-RTC-WBTA-ADC-T-RGB-CSI2-HS-I-01D2
7 * DHCOM PCB number: 660-100 or newer
8 * PDK2 PCB number: 516-400 or newer
11 /dts-v1/;
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/phy/phy-imx8-pcie.h>
15 #include "imx8mp-dhcom-som.dtsi"
19 compatible = "dh,imx8mp-dhcom-pdk2", "dh,imx8mp-dhcom-som",
23 stdout-path = &uart1;
[all …]
Dimx8mm-venice-gw75xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
11 led-controller {
12 compatible = "gpio-leds";
13 pinctrl-names = "default";
14 pinctrl-0 = <&pinctrl_gpio_leds>;
16 led-0 {
20 default-state = "on";
[all …]
Dimx8mm-tqma8mqml-mba8mx.dts1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2020-2021 TQ-Systems GmbH
6 /dts-v1/;
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 #include "imx8mm-tqma8mqml.dtsi"
14 model = "TQ-Systems GmbH i.MX8MM TQMa8MxML on MBa8Mx";
15 compatible = "tq,imx8mm-tqma8mqml-mba8mx", "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
16 chassis-type = "embedded";
27 reg_usdhc2_vmmc: regulator-vmmc {
28 compatible = "regulator-fixed";
[all …]
Dimx8mp-dhcom-pdk3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 * DHCM-iMX8ML8-C160-R409-F1638-SPI16-GE-CAN2-SD-RTC-WBTA-ADC-T-RGB-CSI2-HS-I-01D2
7 * DHCOM PCB number: 660-100 or newer
8 * PDK3 PCB number: 669-100 or newer
11 /dts-v1/;
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/phy/phy-imx8-pcie.h>
15 #include "imx8mp-dhcom-som.dtsi"
19 compatible = "dh,imx8mp-dhcom-pdk3", "dh,imx8mp-dhcom-som",
23 stdout-path = &uart1;
[all …]
Dimx8mp-venice-gw72xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
16 compatible = "gpio-usb-b-connector", "usb-b-connector";
17 pinctrl-names = "default";
18 pinctrl-0 = <&pinctrl_usbcon1>;
21 vbus-supply = <&reg_usb1_vbus>;
22 id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
26 remote-endpoint = <&usb3_dwc>;
[all …]
Dimx8mm-venice-gw7903.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
17 compatible = "gw,imx8mm-gw7903", "fsl,imx8mm";
25 stdout-path = &uart2;
33 gpio-keys {
34 compatible = "gpio-keys";
[all …]
Dimx8mm-venice-gw7904.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
17 compatible = "gateworks,imx8mm-gw7904", "fsl,imx8mm";
20 stdout-path = &uart2;
28 gpio-keys {
29 compatible = "gpio-keys";
[all …]
Dimx8mp-venice-gw73xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
16 compatible = "gpio-usb-b-connector", "usb-b-connector";
17 pinctrl-names = "default";
18 pinctrl-0 = <&pinctrl_usbcon1>;
21 vbus-supply = <&reg_usb1_vbus>;
22 id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
26 remote-endpoint = <&usb3_dwc>;
[all …]
/linux-6.12.1/drivers/phy/intel/
Dphy-intel-lgm-combo.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Combo-PHY driver
5 * Copyright (C) 2019-2020 Intel Corporation.
20 #include <dt-bindings/phy/phy.h>
37 #define COMBO_PHY_ID(x) ((x)->parent->id)
38 #define PHY_ID(x) ((x)->id)
55 * for ComboPhy according to the mode.
63 /* ComboPhy mode Register values */
107 struct intel_combo_phy *cbphy = iphy->parent; in intel_cbphy_iphy_enable()
108 u32 mask = BIT(cbphy->phy_mode * 2 + iphy->id); in intel_cbphy_iphy_enable()
[all …]
/linux-6.12.1/drivers/phy/rockchip/
Dphy-rockchip-usbdp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2021-2024 Rockchip Electronics Co., Ltd
9 #include <dt-bindings/phy/phy.h>
115 /* u2phy-grf */
119 /* usb-grf */
123 /* usbdpphy-grf */
129 /* vo-grf */
168 struct clk *refclk; member
175 u8 mode; member
179 bool hs; /* flag for high-speed */
[all …]

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