bindings/phy/fsl%2Cimx8-pcie-phy.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Richard Zhu <hongxing.zhu@nxp.com>
13   "#phy-cells":
18       - fsl,imx8mm-pcie-phy
19       - fsl,imx8mp-pcie-phy
27   clock-names:
29       - const: ref
35   reset-names:
37       - items:          # for iMX8MM
38           - const: pciephy
39       - items:          # for IMX8MP
40           - const: pciephy
41           - const: perst
43   fsl,refclk-pad-mode:
45       Specifies the mode of the refclk pad used. It can be UNUSED(PHY
47       is provided externally via the refclk pad) or OUTPUT(PHY refclock
48       is derived from SoC internal source and provided on the refclk pad).
49       Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants
54   fsl,tx-deemph-gen1:
55     description: Gen1 De-emphasis value (optional).
59   fsl,tx-deemph-gen2:
60     description: Gen2 De-emphasis value (optional).
64   fsl,clkreq-unsupported:
69   power-domains:
74   - "#phy-cells"
75   - compatible
76   - reg
77   - clocks
78   - clock-names
79   - fsl,refclk-pad-mode
84   - |
85     #include <dt-bindings/clock/imx8mm-clock.h>
86     #include <dt-bindings/phy/phy-imx8-pcie.h>
87     #include <dt-bindings/reset/imx8mq-reset.h>
89     pcie_phy: pcie-phy@32f00000 {
90             compatible = "fsl,imx8mm-pcie-phy";
93             clock-names = "ref";
94             assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
95             assigned-clock-rates = <100000000>;
96             assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
98             reset-names = "pciephy";
99             fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
100             #phy-cells = <0>;