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/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_cdclk.c2 * Copyright © 2006-2017 Intel Corporation
58 * CDCLK clocks most of the display pipe logic, and thus its frequency
63 * On several platforms the CDCLK frequency can be changed dynamically
65 * Typically changes to the CDCLK frequency require all the display pipes
66 * to be shut down while the frequency is being changed.
69 * DMC will not change the active CDCLK frequency however, so that part
73 * frequency:
75 * - We have the CDCLK PLL, which generates an output clock based on a
77 * - The CD2X Divider, which divides the output of the PLL based on a
78 * divisor selected from a set of pre-defined choices.
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/usb/
Docteon-usb.txt7 - compatible: must be "cavium,octeon-5750-usbn"
9 - reg: specifies the physical base address of the USBN block and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
21 - clock-frequency: speed of the USB reference clock. Allowed values are
24 - cavium,refclk-type: type of the USB reference clock. Allowed values are
27 - refclk-frequency: deprecated, use "clock-frequency".
29 - refclk-type: deprecated, use "cavium,refclk-type".
33 The main node must have one child node which describes the built-in
[all …]
Dsmsc,usb3503.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SMSC USB3503 High-Speed Hub Controller
10 - Dongjin Kim <tobetter@gmail.com>
15 - smsc,usb3503
16 - smsc,usb3503a
17 - smsc,usb3803
22 connect-gpios:
27 intn-gpios:
[all …]
Ddwc3-cavium.txt4 - compatible: Should contain "cavium,octeon-7130-usb-uctl"
13 compatible = "cavium,octeon-7130-usb-uctl";
16 #address-cells = <0x00000002>;
17 #size-cells = <0x00000002>;
18 refclk-frequency = <0x05f5e100>;
19 refclk-type-ss = "dlmc_ref_clk0";
20 refclk-type-hs = "dlmc_ref_clk0";
23 compatible = "cavium,octeon-7130-xhci", "snps,dwc3";
25 interrupt-parent = <0x00000010>;
Dti,am62-usb.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/usb/ti,am62-usb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI's AM62 wrapper module for the Synopsys USBSS-DRD controller
10 - Aswath Govindraju <a-govindraju@ti.com>
14 const: ti,am62-usb
19 - description: USB CFG register space
20 - description: USB PHY2 register space
24 power-domains:
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/mips/cavium/
Ductl.txt4 - compatible: "cavium,octeon-6335-uctl"
8 - reg: The base address of the UCTL register bank.
10 - #address-cells: Must be <2>.
12 - #size-cells: Must be <2>.
14 - ranges: Empty to signify direct mapping of the children.
16 - refclk-frequency: A single cell containing the reference clock
17 frequency in Hz.
19 - refclk-type: A string describing the reference clock connection
24 compatible = "cavium,octeon-6335-uctl";
27 #address-cells = <2>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/ti/keystone/
Dkeystone-k2hk-evm.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
7 /dts-v1/;
10 #include "keystone-k2hk.dtsi"
13 compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone";
16 reserved-memory {
17 #address-cells = <2>;
18 #size-cells = <2>;
21 dsp_common_memory: dsp-common-memory@81f800000 {
22 compatible = "shared-dma-pool";
[all …]
Dkeystone-k2e-evm.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
7 /dts-v1/;
10 #include "keystone-k2e.dtsi"
13 compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone";
16 reserved-memory {
17 #address-cells = <2>;
18 #size-cells = <2>;
21 dsp_common_memory: dsp-common-memory@81f800000 {
22 compatible = "shared-dma-pool";
[all …]
/linux-6.12.1/drivers/gpu/drm/loongson/
Dlsdc_pixpll.h1 /* SPDX-License-Identifier: GPL-2.0+ */
14 * refclk: reference frequency, 100 MHz from external oscillator
15 * outclk: output frequency desired.
19 * refclk +-----------+ +------------------+ +---------+ outclk
20 * ---+---> | Prescaler | ---> | Clock Multiplier | ---> | divider | -------->
21 * | +-----------+ +------------------+ +---------+ ^
27 * +---- bypass (bypass above software configurable clock if set) ----+
29 * outclk = refclk / div_ref * loopc / div_out;
38 * 1) 20 MHz <= refclk / div_ref <= 40Mhz
39 * 2) 1.2 GHz <= refclk /div_out * loopc <= 3.2 Ghz
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dnuvoton,npcm750-clk.txt17 dt-bindings/clock/nuvoton,npcm7xx-clock.h
22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
25 - reg: physical base address of the clock controller and length of
28 - #clock-cells: should be 1.
32 clk: clock-controller@f0801000 {
33 compatible = "nuvoton,npcm750-clk";
34 #clock-cells = <1>;
36 clock-names = "refclk", "sysbypck", "mcbypck";
43 clk_refclk: clk-refclk {
44 compatible = "fixed-clock";
[all …]
/linux-6.12.1/drivers/spi/
Dspi-zynq-qspi.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include <linux/spi/spi-mem.h>
28 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst, WO */
29 #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst, WO */
30 #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst, WO */
31 #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst, WO */
57 * QSPI Configuration Register - Baud rate and target select
121 * struct zynq_qspi - Defines qspi driver instance
124 * @refclk: Pointer to the peripheral clock
136 struct clk *refclk; member
[all …]
Dspi-zynqmp-gqspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
6 * Copyright (C) 2009 - 2015 Xilinx, Inc.
11 #include <linux/dma-mapping.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
23 #include <linux/spi/spi-mem.h>
120 #define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
161 * struct qspi_platform_data - zynqmp qspi platform data structure
169 * struct zynqmp_qspi - Defines qspi driver instance
172 * @refclk: Pointer to the peripheral clock
[all …]
/linux-6.12.1/arch/mips/boot/dts/cavium-octeon/
Dubnt_e100.dts1 // SPDX-License-Identifier: GPL-2.0-only
15 phy5: ethernet-phy@5 {
17 compatible = "ethernet-phy-ieee802.3-c22";
19 phy6: ethernet-phy@6 {
21 compatible = "ethernet-phy-ieee802.3-c22";
23 phy7: ethernet-phy@7 {
25 compatible = "ethernet-phy-ieee802.3-c22";
32 phy-handle = <&phy7>;
33 rx-delay = <0>;
34 tx-delay = <0x10>;
[all …]
Ddlink_dsr-500n-1000n.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device tree source for D-Link DSR-500N/1000N (common parts).
13 phy8: ethernet-phy@8 {
15 compatible = "ethernet-phy-ieee802.3-c22";
22 fixed-link {
24 full-duplex;
28 fixed-link {
30 full-duplex;
34 phy-handle = <&phy8>;
47 refclk-frequency = <12000000>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/media/i2c/
Dtc358743.txt1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
8 - compatible: value should be "toshiba,tc358743"
9 - clocks, clock-names: should contain a phandle link to the reference clock
10 source, the clock input is named "refclk".
14 - reset-gpios: gpio phandle GPIO connected to the reset pin
15 - interrupts: GPIO connected to the interrupt pin
16 - data-lanes: should be <1 2 3 4> for four-lane operation,
17 or <1 2> for two-lane operation
[all …]
Dtoshiba,tc358746.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marco Felsch <kernel@pengutronix.de>
12 description: |-
13 The Toshiba TC358746 converts a parallel video stream into a MIPI CSI-2
14 stream. The direction can be either parallel-in -> csi-out or csi-in ->
15 parallel-out The chip is programmable through I2C and SPI but the SPI
16 interface is only supported in parallel-in -> csi-out mode.
19 parallel-in -> csi-out path.
[all …]
/linux-6.12.1/drivers/media/dvb-frontends/
Dstv6110x.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 u32 refclk; member
36 int (*tuner_set_frequency) (struct dvb_frontend *fe, u32 frequency);
37 int (*tuner_get_frequency) (struct dvb_frontend *fe, u32 *frequency);
42 int (*tuner_set_refclk) (struct dvb_frontend *fe, u32 refclk);
/linux-6.12.1/arch/mips/boot/dts/brcm/
Dbcm6362.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "dt-bindings/clock/bcm6362-clock.h"
4 #include "dt-bindings/reset/bcm6362-reset.h"
5 #include "dt-bindings/soc/bcm6362-pm.h"
8 #address-cells = <1>;
9 #size-cells = <1>;
13 #address-cells = <1>;
14 #size-cells = <0>;
16 mips-hpt-frequency = <200000000>;
32 periph_osc: periph-osc {
[all …]
Dbcm6328.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "dt-bindings/clock/bcm6328-clock.h"
4 #include "dt-bindings/reset/bcm6328-reset.h"
5 #include "dt-bindings/soc/bcm6328-pm.h"
8 #address-cells = <1>;
9 #size-cells = <1>;
13 #address-cells = <1>;
14 #size-cells = <0>;
16 mips-hpt-frequency = <160000000>;
32 periph_osc: periph-osc {
[all …]
Dbcm3368.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "dt-bindings/clock/bcm3368-clock.h"
6 #address-cells = <1>;
7 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
14 mips-hpt-frequency = <150000000>;
30 periph_clk: periph-clk {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
[all …]
Dbcm6358.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "dt-bindings/clock/bcm6358-clock.h"
4 #include "dt-bindings/reset/bcm6358-reset.h"
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
15 mips-hpt-frequency = <150000000>;
31 periph_osc: periph-osc {
32 compatible = "fixed-clock";
[all …]
Dbcm63268.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "dt-bindings/clock/bcm63268-clock.h"
4 #include "dt-bindings/reset/bcm63268-reset.h"
5 #include "dt-bindings/soc/bcm63268-pm.h"
8 #address-cells = <1>;
9 #size-cells = <1>;
13 #address-cells = <1>;
14 #size-cells = <0>;
16 mips-hpt-frequency = <200000000>;
32 periph_osc: periph-osc {
[all …]
Dbcm6368.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "dt-bindings/clock/bcm6368-clock.h"
4 #include "dt-bindings/reset/bcm6368-reset.h"
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
15 mips-hpt-frequency = <200000000>;
31 periph_osc: periph-osc {
32 compatible = "fixed-clock";
[all …]
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dimx8mm-venice-gw71xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
16 led-controller {
17 compatible = "gpio-leds";
18 pinctrl-names = "default";
19 pinctrl-0 = <&pinctrl_gpio_leds>;
21 led-0 {
25 default-state = "on";
[all …]
/linux-6.12.1/drivers/clk/analogbits/
Dwrpll-cln28hpc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
33 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
35 /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
38 /* MAX_INPUT_FREQ: maximum input clock frequency, in Hz (Fref_max) */
41 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
[all …]

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