Lines Matching +full:refclk +full:- +full:frequency
1 // SPDX-License-Identifier: GPL-2.0+
18 #include <linux/spi/spi-mem.h>
28 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst, WO */
29 #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst, WO */
30 #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst, WO */
31 #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst, WO */
57 * QSPI Configuration Register - Baud rate and target select
121 * struct zynq_qspi - Defines qspi driver instance
124 * @refclk: Pointer to the peripheral clock
136 struct clk *refclk; member
151 return readl_relaxed(xqspi->regs + offset); in zynq_qspi_read()
157 writel_relaxed(val, xqspi->regs + offset); in zynq_qspi_write()
161 * zynq_qspi_init_hw - Initialize the hardware
167 * - Host mode
168 * - Baud rate divisor is set to 2
169 * - Tx threshold set to 1l Rx threshold set to 32
170 * - Flash memory interface mode enabled
171 * - Size of the word to be transferred as 8 bit
173 * - Disable and clear all the interrupts
174 * - Enable manual target select
175 * - Enable manual start
176 * - Deselect all the chip select lines
177 * - Set the size of the word to be transferred as 32 bit
178 * - Set the little endian mode of TX FIFO and
179 * - Enable the QSPI controller
234 if (op->addr.nbytes > 3) in zynq_qspi_supports_op()
241 * zynq_qspi_rxfifo_op - Read 1..4 bytes from RxFIFO to RX buffer
251 if (xqspi->rxbuf) { in zynq_qspi_rxfifo_op()
252 memcpy(xqspi->rxbuf, ((u8 *)&data) + 4 - size, size); in zynq_qspi_rxfifo_op()
253 xqspi->rxbuf += size; in zynq_qspi_rxfifo_op()
256 xqspi->rx_bytes -= size; in zynq_qspi_rxfifo_op()
257 if (xqspi->rx_bytes < 0) in zynq_qspi_rxfifo_op()
258 xqspi->rx_bytes = 0; in zynq_qspi_rxfifo_op()
262 * zynq_qspi_txfifo_op - Write 1..4 bytes from TX buffer to TxFIFO
273 if (xqspi->txbuf) { in zynq_qspi_txfifo_op()
275 memcpy(&data, xqspi->txbuf, size); in zynq_qspi_txfifo_op()
276 xqspi->txbuf += size; in zynq_qspi_txfifo_op()
281 xqspi->tx_bytes -= size; in zynq_qspi_txfifo_op()
282 zynq_qspi_write(xqspi, offset[size - 1], data); in zynq_qspi_txfifo_op()
286 * zynq_qspi_chipselect - Select or deselect the chip select line
292 struct spi_controller *ctlr = spi->controller; in zynq_qspi_chipselect()
297 if (ctlr->num_chipselect > 1) { in zynq_qspi_chipselect()
318 * zynq_qspi_config_op - Configure QSPI controller for specified transfer
323 * sets the requested clock frequency.
325 * Return: 0 on success and -EINVAL on invalid input parameter
327 * Note: If the requested frequency is not an exact match with what can be
328 * obtained using the prescalar value, the driver sets the clock frequency which
329 * is lower than the requested frequency (maximum lower) for the transfer. If
330 * the requested frequency is higher or lower than that is supported by the QSPI
331 * controller the driver will set the highest or lowest frequency supported by
339 * Set the clock frequency in zynq_qspi_config_op()
342 * i.e. 000 - divide by 2 in zynq_qspi_config_op()
343 * 001 - divide by 4 in zynq_qspi_config_op()
344 * ---------------- in zynq_qspi_config_op()
345 * 111 - divide by 256 in zynq_qspi_config_op()
348 (clk_get_rate(xqspi->refclk) / (2 << baud_rate_val)) > in zynq_qspi_config_op()
349 spi->max_speed_hz) in zynq_qspi_config_op()
357 if (spi->mode & SPI_CPHA) in zynq_qspi_config_op()
359 if (spi->mode & SPI_CPOL) in zynq_qspi_config_op()
370 * zynq_qspi_setup_op - Configure the QSPI controller
380 struct spi_controller *ctlr = spi->controller; in zynq_qspi_setup_op()
383 if (ctlr->busy) in zynq_qspi_setup_op()
384 return -EBUSY; in zynq_qspi_setup_op()
386 clk_enable(qspi->refclk); in zynq_qspi_setup_op()
387 clk_enable(qspi->pclk); in zynq_qspi_setup_op()
395 * zynq_qspi_write_op - Fills the TX FIFO with as many bytes as possible
405 len = xqspi->tx_bytes; in zynq_qspi_write_op()
421 if (xqspi->txbuf) { in zynq_qspi_write_op()
422 iowrite32_rep(xqspi->regs + ZYNQ_QSPI_TXD_00_00_OFFSET, in zynq_qspi_write_op()
423 xqspi->txbuf, count); in zynq_qspi_write_op()
424 xqspi->txbuf += count * 4; in zynq_qspi_write_op()
427 writel_relaxed(0, xqspi->regs + in zynq_qspi_write_op()
431 xqspi->tx_bytes -= count * 4; in zynq_qspi_write_op()
435 * zynq_qspi_read_op - Drains the RX FIFO by as many bytes as possible
443 len = xqspi->rx_bytes - xqspi->tx_bytes; in zynq_qspi_read_op()
447 if (xqspi->rxbuf) { in zynq_qspi_read_op()
448 ioread32_rep(xqspi->regs + ZYNQ_QSPI_RXD_OFFSET, in zynq_qspi_read_op()
449 xqspi->rxbuf, count); in zynq_qspi_read_op()
450 xqspi->rxbuf += count * 4; in zynq_qspi_read_op()
453 readl_relaxed(xqspi->regs + ZYNQ_QSPI_RXD_OFFSET); in zynq_qspi_read_op()
455 xqspi->rx_bytes -= count * 4; in zynq_qspi_read_op()
456 len -= count * 4; in zynq_qspi_read_op()
463 * zynq_qspi_irq - Interrupt service routine of the QSPI controller
492 if (xqspi->tx_bytes) { in zynq_qspi_irq()
501 if (!xqspi->rx_bytes) { in zynq_qspi_irq()
505 complete(&xqspi->data_completion); in zynq_qspi_irq()
515 * zynq_qspi_exec_mem_op() - Initiates the QSPI transfer
528 struct zynq_qspi *xqspi = spi_controller_get_devdata(mem->spi->controller); in zynq_qspi_exec_mem_op()
532 dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n", in zynq_qspi_exec_mem_op()
533 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth, in zynq_qspi_exec_mem_op()
534 op->dummy.buswidth, op->data.buswidth); in zynq_qspi_exec_mem_op()
536 zynq_qspi_chipselect(mem->spi, true); in zynq_qspi_exec_mem_op()
537 zynq_qspi_config_op(xqspi, mem->spi); in zynq_qspi_exec_mem_op()
539 if (op->cmd.opcode) { in zynq_qspi_exec_mem_op()
540 reinit_completion(&xqspi->data_completion); in zynq_qspi_exec_mem_op()
541 xqspi->txbuf = (u8 *)&op->cmd.opcode; in zynq_qspi_exec_mem_op()
542 xqspi->rxbuf = NULL; in zynq_qspi_exec_mem_op()
543 xqspi->tx_bytes = op->cmd.nbytes; in zynq_qspi_exec_mem_op()
544 xqspi->rx_bytes = op->cmd.nbytes; in zynq_qspi_exec_mem_op()
548 if (!wait_for_completion_timeout(&xqspi->data_completion, in zynq_qspi_exec_mem_op()
550 err = -ETIMEDOUT; in zynq_qspi_exec_mem_op()
553 if (op->addr.nbytes) { in zynq_qspi_exec_mem_op()
554 for (i = 0; i < op->addr.nbytes; i++) { in zynq_qspi_exec_mem_op()
555 xqspi->txbuf[i] = op->addr.val >> in zynq_qspi_exec_mem_op()
556 (8 * (op->addr.nbytes - i - 1)); in zynq_qspi_exec_mem_op()
559 reinit_completion(&xqspi->data_completion); in zynq_qspi_exec_mem_op()
560 xqspi->rxbuf = NULL; in zynq_qspi_exec_mem_op()
561 xqspi->tx_bytes = op->addr.nbytes; in zynq_qspi_exec_mem_op()
562 xqspi->rx_bytes = op->addr.nbytes; in zynq_qspi_exec_mem_op()
566 if (!wait_for_completion_timeout(&xqspi->data_completion, in zynq_qspi_exec_mem_op()
568 err = -ETIMEDOUT; in zynq_qspi_exec_mem_op()
571 if (op->dummy.nbytes) { in zynq_qspi_exec_mem_op()
572 tmpbuf = kmalloc(op->dummy.nbytes, GFP_KERNEL); in zynq_qspi_exec_mem_op()
574 return -ENOMEM; in zynq_qspi_exec_mem_op()
576 memset(tmpbuf, 0xff, op->dummy.nbytes); in zynq_qspi_exec_mem_op()
577 reinit_completion(&xqspi->data_completion); in zynq_qspi_exec_mem_op()
578 xqspi->txbuf = tmpbuf; in zynq_qspi_exec_mem_op()
579 xqspi->rxbuf = NULL; in zynq_qspi_exec_mem_op()
580 xqspi->tx_bytes = op->dummy.nbytes; in zynq_qspi_exec_mem_op()
581 xqspi->rx_bytes = op->dummy.nbytes; in zynq_qspi_exec_mem_op()
585 if (!wait_for_completion_timeout(&xqspi->data_completion, in zynq_qspi_exec_mem_op()
587 err = -ETIMEDOUT; in zynq_qspi_exec_mem_op()
592 if (op->data.nbytes) { in zynq_qspi_exec_mem_op()
593 reinit_completion(&xqspi->data_completion); in zynq_qspi_exec_mem_op()
594 if (op->data.dir == SPI_MEM_DATA_OUT) { in zynq_qspi_exec_mem_op()
595 xqspi->txbuf = (u8 *)op->data.buf.out; in zynq_qspi_exec_mem_op()
596 xqspi->tx_bytes = op->data.nbytes; in zynq_qspi_exec_mem_op()
597 xqspi->rxbuf = NULL; in zynq_qspi_exec_mem_op()
598 xqspi->rx_bytes = op->data.nbytes; in zynq_qspi_exec_mem_op()
600 xqspi->txbuf = NULL; in zynq_qspi_exec_mem_op()
601 xqspi->rxbuf = (u8 *)op->data.buf.in; in zynq_qspi_exec_mem_op()
602 xqspi->rx_bytes = op->data.nbytes; in zynq_qspi_exec_mem_op()
603 xqspi->tx_bytes = op->data.nbytes; in zynq_qspi_exec_mem_op()
609 if (!wait_for_completion_timeout(&xqspi->data_completion, in zynq_qspi_exec_mem_op()
611 err = -ETIMEDOUT; in zynq_qspi_exec_mem_op()
613 zynq_qspi_chipselect(mem->spi, false); in zynq_qspi_exec_mem_op()
624 * zynq_qspi_probe - Probe method for the QSPI driver
635 struct device *dev = &pdev->dev; in zynq_qspi_probe()
636 struct device_node *np = dev->of_node; in zynq_qspi_probe()
640 ctlr = spi_alloc_host(&pdev->dev, sizeof(*xqspi)); in zynq_qspi_probe()
642 return -ENOMEM; in zynq_qspi_probe()
645 xqspi->dev = dev; in zynq_qspi_probe()
647 xqspi->regs = devm_platform_ioremap_resource(pdev, 0); in zynq_qspi_probe()
648 if (IS_ERR(xqspi->regs)) { in zynq_qspi_probe()
649 ret = PTR_ERR(xqspi->regs); in zynq_qspi_probe()
653 xqspi->pclk = devm_clk_get(&pdev->dev, "pclk"); in zynq_qspi_probe()
654 if (IS_ERR(xqspi->pclk)) { in zynq_qspi_probe()
655 dev_err(&pdev->dev, "pclk clock not found.\n"); in zynq_qspi_probe()
656 ret = PTR_ERR(xqspi->pclk); in zynq_qspi_probe()
660 init_completion(&xqspi->data_completion); in zynq_qspi_probe()
662 xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk"); in zynq_qspi_probe()
663 if (IS_ERR(xqspi->refclk)) { in zynq_qspi_probe()
664 dev_err(&pdev->dev, "ref_clk clock not found.\n"); in zynq_qspi_probe()
665 ret = PTR_ERR(xqspi->refclk); in zynq_qspi_probe()
669 ret = clk_prepare_enable(xqspi->pclk); in zynq_qspi_probe()
671 dev_err(&pdev->dev, "Unable to enable APB clock.\n"); in zynq_qspi_probe()
675 ret = clk_prepare_enable(xqspi->refclk); in zynq_qspi_probe()
677 dev_err(&pdev->dev, "Unable to enable device clock.\n"); in zynq_qspi_probe()
681 xqspi->irq = platform_get_irq(pdev, 0); in zynq_qspi_probe()
682 if (xqspi->irq < 0) { in zynq_qspi_probe()
683 ret = xqspi->irq; in zynq_qspi_probe()
686 ret = devm_request_irq(&pdev->dev, xqspi->irq, zynq_qspi_irq, in zynq_qspi_probe()
687 0, pdev->name, xqspi); in zynq_qspi_probe()
689 ret = -ENXIO; in zynq_qspi_probe()
690 dev_err(&pdev->dev, "request_irq failed\n"); in zynq_qspi_probe()
694 ret = of_property_read_u32(np, "num-cs", in zynq_qspi_probe()
697 ctlr->num_chipselect = 1; in zynq_qspi_probe()
699 ret = -EINVAL; in zynq_qspi_probe()
700 dev_err(&pdev->dev, "only 2 chip selects are available\n"); in zynq_qspi_probe()
703 ctlr->num_chipselect = num_cs; in zynq_qspi_probe()
706 ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | in zynq_qspi_probe()
708 ctlr->mem_ops = &zynq_qspi_mem_ops; in zynq_qspi_probe()
709 ctlr->setup = zynq_qspi_setup_op; in zynq_qspi_probe()
710 ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2; in zynq_qspi_probe()
711 ctlr->dev.of_node = np; in zynq_qspi_probe()
714 zynq_qspi_init_hw(xqspi, ctlr->num_chipselect); in zynq_qspi_probe()
716 ret = devm_spi_register_controller(&pdev->dev, ctlr); in zynq_qspi_probe()
718 dev_err(&pdev->dev, "devm_spi_register_controller failed\n"); in zynq_qspi_probe()
725 clk_disable_unprepare(xqspi->refclk); in zynq_qspi_probe()
727 clk_disable_unprepare(xqspi->pclk); in zynq_qspi_probe()
735 * zynq_qspi_remove - Remove method for the QSPI driver
750 clk_disable_unprepare(xqspi->refclk); in zynq_qspi_remove()
751 clk_disable_unprepare(xqspi->pclk); in zynq_qspi_remove()
755 { .compatible = "xlnx,zynq-qspi-1.0", },
762 * zynq_qspi_driver - This structure defines the QSPI platform driver
768 .name = "zynq-qspi",