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Searched +full:r9a09g057 +full:- +full:cpg (Results 1 – 12 of 12) sorted by relevance

/linux-6.12.1/arch/arm64/boot/dts/renesas/
Dr9a09g057.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "renesas,r9a09g057";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_extal_clk: audio-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
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Dr9a08g045.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a08g045-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "arm,cortex-a55";
24 #cooling-cells = <2>;
25 next-level-cache = <&L3_CA55>;
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/linux-6.12.1/Documentation/devicetree/bindings/clock/
Drenesas,rzv2h-cpg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
13 On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
19 const: renesas,r9a09g057-cpg
26 - description: AUDIO_EXTAL clock input
27 - description: RTXIN clock input
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/linux-6.12.1/Documentation/devicetree/bindings/soc/renesas/
Drenesas,r9a09g057-sys.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/renesas/renesas,r9a09g057-sys.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
15 - Trust zone control
16 - Extend access by specific masters to address beyond 4GB space
17 - GBETH configuration
18 - Control of settings and states of SRAM/PCIe/CM33/CA55/CR8/xSPI/ADC/TSU
19 - LSI version
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/linux-6.12.1/Documentation/devicetree/bindings/watchdog/
Drenesas,wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfram Sang <wsa+renesas@sang-engineering.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 - items:
17 - enum:
18 - renesas,r7s72100-wdt # RZ/A1
19 - renesas,r7s9210-wdt # RZ/A2
20 - const: renesas,rza-wdt # RZ/A
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/linux-6.12.1/Documentation/devicetree/bindings/serial/
Drenesas,scif.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
15 - items:
16 - enum:
17 - renesas,scif-r7s72100 # RZ/A1H
18 - const: renesas,scif # generic SCIF compatible UART
20 - items:
21 - enum:
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/linux-6.12.1/Documentation/devicetree/bindings/pinctrl/
Drenesas,rzg2l-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
24 - items:
25 - enum:
26 - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
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/linux-6.12.1/Documentation/devicetree/bindings/mmc/
Drenesas,sdhi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfram Sang <wsa+renesas@sang-engineering.com>
15 - enum:
16 - renesas,sdhi-mmc-r8a77470 # RZ/G1C
17 - renesas,sdhi-r7s72100 # RZ/A1H
18 - renesas,sdhi-r7s9210 # SH-Mobile AG5
19 - renesas,sdhi-r8a73a4 # R-Mobile APE6
20 - renesas,sdhi-r8a7740 # R-Mobile A1
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/linux-6.12.1/drivers/clk/renesas/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 obj-$(CONFIG_CLK_EMEV2) += clk-emev2.o
4 obj-$(CONFIG_CLK_RZA1) += clk-rz.o
5 obj-$(CONFIG_CLK_R7S9210) += r7s9210-cpg-mssr.o
6 obj-$(CONFIG_CLK_R8A73A4) += clk-r8a73a4.o
7 obj-$(CONFIG_CLK_R8A7740) += clk-r8a7740.o
8 obj-$(CONFIG_CLK_R8A7742) += r8a7742-cpg-mssr.o
9 obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
10 obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
11 obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
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Dr9a09g057-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RZ/V2H(P) CPG driver
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
Drzv2h-cpg.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on rzg2l-cpg.c
16 #include <linux/clk-provider.h>
26 #include <linux/reset-controller.h>
28 #include <dt-bindings/clock/renesas-cpg-mssr.h>
30 #include "rzv2h-cpg.h"
56 * struct rzv2h_cpg_priv - Clock Pulse Generator Private Data
58 * @dev: CPG device
59 * @base: CPG register block base address
65 * @num_resets: Number of Module Resets in info->resets[]
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/linux-6.12.1/drivers/watchdog/
Drzv2h_wdt.c1 // SPDX-License-Identifier: GPL-2.0
61 * The down-counter is refreshed and starts counting operation on in rzv2h_wdt_ping()
64 writeb(0x0, priv->base + WDTRR); in rzv2h_wdt_ping()
65 writeb(0xFF, priv->base + WDTRR); in rzv2h_wdt_ping()
75 writew(wdtcr, priv->base + WDTCR); in rzv2h_wdt_setup()
78 writeb(0, priv->base + WDTRCR); in rzv2h_wdt_setup()
81 writew(0, priv->base + WDTSR); in rzv2h_wdt_setup()
89 ret = pm_runtime_resume_and_get(wdev->parent); in rzv2h_wdt_start()
93 ret = reset_control_deassert(priv->rstc); in rzv2h_wdt_start()
95 pm_runtime_put(wdev->parent); in rzv2h_wdt_start()
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