Lines Matching +full:r9a09g057 +full:- +full:cpg
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a08g045-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "arm,cortex-a55";
24 #cooling-cells = <2>;
25 next-level-cache = <&L3_CA55>;
26 enable-method = "psci";
27 clocks = <&cpg CPG_CORE R9A08G045_CLK_I>;
30 L3_CA55: cache-controller-0 {
32 cache-level = <3>;
33 cache-unified;
34 cache-size = <0x40000>;
38 extal_clk: extal-clk {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
42 clock-frequency = <0>;
46 compatible = "arm,psci-1.0", "arm,psci-0.2";
51 compatible = "simple-bus";
52 interrupt-parent = <&gic>;
53 #address-cells = <2>;
54 #size-cells = <2>;
58 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
66 interrupt-names = "eri", "rxi", "txi",
68 clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>;
69 clock-names = "fck";
70 power-domains = <&cpg>;
71 resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>;
76 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
86 interrupt-names = "tei", "ri", "ti", "spi", "sti",
88 clocks = <&cpg CPG_MOD R9A08G045_I2C0_PCLK>;
89 clock-frequency = <100000>;
90 resets = <&cpg R9A08G045_I2C0_MRST>;
91 power-domains = <&cpg>;
92 #address-cells = <1>;
93 #size-cells = <0>;
98 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
108 interrupt-names = "tei", "ri", "ti", "spi", "sti",
110 clocks = <&cpg CPG_MOD R9A08G045_I2C1_PCLK>;
111 clock-frequency = <100000>;
112 resets = <&cpg R9A08G045_I2C1_MRST>;
113 power-domains = <&cpg>;
114 #address-cells = <1>;
115 #size-cells = <0>;
120 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
130 interrupt-names = "tei", "ri", "ti", "spi", "sti",
132 clocks = <&cpg CPG_MOD R9A08G045_I2C2_PCLK>;
133 clock-frequency = <100000>;
134 resets = <&cpg R9A08G045_I2C2_MRST>;
135 power-domains = <&cpg>;
136 #address-cells = <1>;
137 #size-cells = <0>;
142 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
152 interrupt-names = "tei", "ri", "ti", "spi", "sti",
154 clocks = <&cpg CPG_MOD R9A08G045_I2C3_PCLK>;
155 clock-frequency = <100000>;
156 resets = <&cpg R9A08G045_I2C3_MRST>;
157 power-domains = <&cpg>;
158 #address-cells = <1>;
159 #size-cells = <0>;
163 cpg: clock-controller@11010000 { label
164 compatible = "renesas,r9a08g045-cpg";
167 clock-names = "extal";
168 #clock-cells = <2>;
169 #reset-cells = <1>;
170 #power-domain-cells = <0>;
173 sysc: system-controller@11020000 {
174 compatible = "renesas,r9a08g045-sysc";
180 interrupt-names = "lpm_int", "ca55stbydone_int",
186 compatible = "renesas,r9a08g045-pinctrl";
188 gpio-controller;
189 #gpio-cells = <2>;
190 interrupt-controller;
191 #interrupt-cells = <2>;
192 interrupt-parent = <&irqc>;
193 gpio-ranges = <&pinctrl 0 0 152>;
194 clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>;
195 power-domains = <&cpg>;
196 resets = <&cpg R9A08G045_GPIO_RSTN>,
197 <&cpg R9A08G045_GPIO_PORT_RESETN>,
198 <&cpg R9A08G045_GPIO_SPARE_RESETN>;
201 irqc: interrupt-controller@11050000 {
202 compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc";
203 #interrupt-cells = <2>;
204 #address-cells = <0>;
205 interrupt-controller;
252 interrupt-names = "nmi",
263 "bus-err", "ec7tie1-0", "ec7tie2-0",
264 "ec7tiovf-0";
265 clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
266 <&cpg CPG_MOD R9A08G045_IA55_PCLK>;
267 clock-names = "clk", "pclk";
268 power-domains = <&cpg>;
269 resets = <&cpg R9A08G045_IA55_RESETN>;
272 dmac: dma-controller@11820000 {
273 compatible = "renesas,r9a08g045-dmac",
274 "renesas,rz-dmac";
294 interrupt-names = "error",
299 clocks = <&cpg CPG_MOD R9A08G045_DMAC_ACLK>,
300 <&cpg CPG_MOD R9A08G045_DMAC_PCLK>;
301 clock-names = "main", "register";
302 power-domains = <&cpg>;
303 resets = <&cpg R9A08G045_DMAC_ARESETN>,
304 <&cpg R9A08G045_DMAC_RST_ASYNC>;
305 reset-names = "arst", "rst_async";
306 #dma-cells = <1>;
307 dma-channels = <16>;
311 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi";
315 clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>,
316 <&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>,
317 <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>,
318 <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>;
319 clock-names = "core", "clkh", "cd", "aclk";
320 resets = <&cpg R9A08G045_SDHI0_IXRST>;
321 power-domains = <&cpg>;
326 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi";
330 clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>,
331 <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>,
332 <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>,
333 <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>;
334 clock-names = "core", "clkh", "cd", "aclk";
335 resets = <&cpg R9A08G045_SDHI1_IXRST>;
336 power-domains = <&cpg>;
341 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi";
345 clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>,
346 <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>,
347 <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>,
348 <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>;
349 clock-names = "core", "clkh", "cd", "aclk";
350 resets = <&cpg R9A08G045_SDHI2_IXRST>;
351 power-domains = <&cpg>;
356 compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
361 interrupt-names = "mux", "fil", "arp_ns";
362 phy-mode = "rgmii";
363 clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>,
364 <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>,
365 <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>;
366 clock-names = "axi", "chi", "refclk";
367 resets = <&cpg R9A08G045_ETH0_RST_HW_N>;
368 power-domains = <&cpg>;
369 #address-cells = <1>;
370 #size-cells = <0>;
375 compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
380 interrupt-names = "mux", "fil", "arp_ns";
381 phy-mode = "rgmii";
382 clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>,
383 <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>,
384 <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>;
385 clock-names = "axi", "chi", "refclk";
386 resets = <&cpg R9A08G045_ETH1_RST_HW_N>;
387 power-domains = <&cpg>;
388 #address-cells = <1>;
389 #size-cells = <0>;
393 gic: interrupt-controller@12400000 {
394 compatible = "arm,gic-v3";
395 #interrupt-cells = <3>;
396 #address-cells = <0>;
397 interrupt-controller;
404 compatible = "renesas,r9a08g045-wdt", "renesas,rzg2l-wdt";
406 clocks = <&cpg CPG_MOD R9A08G045_WDT0_PCLK>,
407 <&cpg CPG_MOD R9A08G045_WDT0_CLK>;
408 clock-names = "pclk", "oscclk";
411 interrupt-names = "wdt", "perrout";
412 resets = <&cpg R9A08G045_WDT0_PRESETN>;
413 power-domains = <&cpg>;
419 compatible = "arm,armv8-timer";
420 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
425 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
426 "hyp-virt";