bindings/pinctrl/renesas%2Crzg2l-pinctrl.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Geert Uytterhoeven <geert+renesas@glider.be>
11   - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
16   Pin multiplexing and GPIO configuration is performed on a per-pin basis.
24       - items:
25           - enum:
26               - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
27               - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
28               - renesas,r9a08g045-pinctrl # RZ/G3S
29               - renesas,r9a09g057-pinctrl # RZ/V2H(P)
31       - items:
32           - enum:
33               - renesas,r9a07g054-pinctrl     # RZ/V2L
34           - const: renesas,r9a07g044-pinctrl  # RZ/G2{L,LC} fallback for RZ/V2L
39   gpio-controller: true
41   '#gpio-cells':
45       RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
49   gpio-ranges:
52   interrupt-controller: true
54   '#interrupt-cells':
58       RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
66   power-domains:
71       - items:
72           - description: GPIO_RSTN signal
73           - description: GPIO_PORT_RESETN signal
74           - description: GPIO_SPARE_RESETN signal
75       - items:
76           - description: PFC main reset
77           - description: Reset for the control register related to WDTUDFCA and WDTUDFFCM pins
81     - type: object
84         - $ref: pincfg-node.yaml#
85         - $ref: pinmux-node.yaml#
97             helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h>.
99         drive-strength:
101         drive-strength-microamp:
105         output-impedance-ohms:
107         power-source:
110         slew-rate: true
111         gpio-hog: true
114         input-enable: true
115         output-enable: true
116         output-high: true
117         output-low: true
118         line-name: true
119         bias-disable: true
120         bias-pull-down: true
121         bias-pull-up: true
122         renesas,output-impedance:
126             register, which adjusts the drive strength value and is pin-dependent.
130     - type: object
135   - $ref: pinctrl.yaml#
137   - if:
141             const: renesas,r9a09g057-pinctrl
152   - compatible
153   - reg
154   - gpio-controller
155   - '#gpio-cells'
156   - gpio-ranges
157   - interrupt-controller
158   - '#interrupt-cells'
159   - clocks
160   - power-domains
161   - resets
164   - |
165     #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
166     #include <dt-bindings/clock/r9a07g044-cpg.h>
169             compatible = "renesas,r9a07g044-pinctrl";
172             gpio-controller;
173             #gpio-cells = <2>;
174             gpio-ranges = <&pinctrl 0 0 392>;
175             interrupt-controller;
176             #interrupt-cells = <2>;
177             clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
178             resets = <&cpg R9A07G044_GPIO_RSTN>,
179                      <&cpg R9A07G044_GPIO_PORT_RESETN>,
180                      <&cpg R9A07G044_GPIO_SPARE_RESETN>;
181             power-domains = <&cpg>;
190                     input-enable;
193             sd1-pwr-en-hog {
194                     gpio-hog;
196                     output-high;
197                     line-name = "sd1_pwr_en";
204                             power-source = <3300>;
209                             power-source = <3300>;
214                             power-source = <3300>;