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/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dsilabs,si5351.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3
16 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
19 - Alvin Šipraga <alsi@bang-olufsen.dk>
24 - silabs,si5351a # Si5351A, 20-QFN package
25 - silabs,si5351a-msop # Si5351A, 10-MSOP package
26 - silabs,si5351b # Si5351B, 20-QFN package
27 - silabs,si5351c # Si5351C, 20-QFN package
[all …]
Dqcom,mmcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeffrey Hugo <quic_jhugo@quicinc.com>
11 - Taniya Das <quic_tdas@quicinc.com>
20 - qcom,mmcc-apq8064
21 - qcom,mmcc-apq8084
22 - qcom,mmcc-msm8226
23 - qcom,mmcc-msm8660
24 - qcom,mmcc-msm8960
[all …]
Dbrcm,iproc-clocks.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/brcm,iproc-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ray Jui <rjui@broadcom.com>
11 - Scott Branden <sbranden@broadcom.com>
16 LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
25 - brcm,bcm63138-armpll
26 - brcm,cygnus-armpll
27 - brcm,cygnus-genpll
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Dbrcm,bcm2835-cprman.txt4 Documentation/devicetree/bindings/clock/clock-bindings.txt
8 oscillator, a level of PLL dividers that produce channels off of the
9 few PLLs, and a level of mostly-generic clock generators sourcing from
10 the PLL channels. Most other hardware components source from the
11 clock generators, but a few (like the ARM or HDMI) will source from
12 the PLL dividers directly.
15 - compatible: should be one of the following,
16 "brcm,bcm2711-cprman"
17 "brcm,bcm2835-cprman"
18 - #clock-cells: Should be <1>. The permitted clock-specifier values can be
[all …]
Dcirrus,cs2000-cp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/cirrus,cs2000-cp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
13 The CS2000-CP is an extremely versatile system clocking device that
21 - cirrus,cs2000-cp
28 clock-names:
30 - const: clk_in
[all …]
/linux-6.12.1/include/linux/platform_data/
Dsi5351.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * enum si5351_pll_src - Si5351 pll clock source
12 * @SI5351_PLL_SRC_XTAL: pll source clock is XTAL input
13 * @SI5351_PLL_SRC_CLKIN: pll source clock is CLKIN input (Si5351C only)
22 * enum si5351_multisynth_src - Si5351 multisynth clock source
24 * @SI5351_MULTISYNTH_SRC_VCO0: multisynth source clock is VCO0
25 * @SI5351_MULTISYNTH_SRC_VCO1: multisynth source clock is VCO1/VXCO
34 * enum si5351_clkout_src - Si5351 clock output clock source
36 * @SI5351_CLKOUT_SRC_MSYNTH_N: clkout N source clock is multisynth N
37 * @SI5351_CLKOUT_SRC_MSYNTH_0_4: clkout N source clock is multisynth 0 (N<4)
[all …]
/linux-6.12.1/drivers/video/fbdev/via/
Dvia_clock.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
8 * clock and PLL management functions
12 #include <linux/via-core.h>
21 static inline u32 cle266_encode_pll(struct via_pll_config pll) in cle266_encode_pll() argument
23 return (pll.multiplier << 8) in cle266_encode_pll()
24 | (pll.rshift << 6) in cle266_encode_pll()
25 | pll.divisor; in cle266_encode_pll()
28 static inline u32 k800_encode_pll(struct via_pll_config pll) in k800_encode_pll() argument
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/linux-6.12.1/Documentation/devicetree/bindings/usb/
Dnvidia,tegra124-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra124-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
20 - description: NVIDIA Tegra124
21 const: nvidia,tegra124-xusb
23 - description: NVIDIA Tegra132
25 - const: nvidia,tegra132-xusb
[all …]
Dnvidia,tegra210-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra210-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
18 const: nvidia,tegra210-xusb
22 - description: base and length of the xHCI host registers
23 - description: base and length of the XUSB FPCI registers
24 - description: base and length of the XUSB IPFS registers
[all …]
Dnvidia,tegra194-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra194-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
18 const: nvidia,tegra194-xusb
22 - description: base and length of the xHCI host registers
23 - description: base and length of the XUSB FPCI registers
25 reg-names:
[all …]
Dnvidia,tegra186-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra186-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
18 const: nvidia,tegra186-xusb
22 - description: base and length of the xHCI host registers
23 - description: base and length of the XUSB FPCI registers
25 reg-names:
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/linux-6.12.1/drivers/clk/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
43 source "drivers/clk/versatile/Kconfig"
46 bool "PLL Driver for HSDK platform"
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
88 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
98 multi-function device has one fixed-rate oscillator, clocked
129 be pre-programmed to support other configurations and features not yet
178 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
196 For example, the CDCE925 contains two PLLs with spread-spectrum
202 Given a target output frequency, the driver will set the PLL and
[all …]
Dclk-k210.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #define pr_fmt(fmt) "k210-clk: " fmt
15 #include <linux/clk-provider.h>
18 #include <soc/canaan/k210-sysctl.h>
20 #include <dt-bindings/clock/k210-clk.h>
253 * PLL control register bits.
268 * PLL lock register bits.
322 * struct k210_sysclk - sysclk driver data
354 struct k210_pll *pll) in k210_init_pll() argument
[all …]
/linux-6.12.1/sound/soc/codecs/
Dadav80x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Lars-Peter Clausen <lars@metafoo.de>
46 #define ADAV80X_PLL_CLK_SRC_PLL_XIN(pll) 0x00 argument
47 #define ADAV80X_PLL_CLK_SRC_PLL_MCLKI(pll) (0x40 << (pll)) argument
48 #define ADAV80X_PLL_CLK_SRC_PLL_MASK(pll) (0x40 << (pll)) argument
56 #define ADAV80X_PLL_CTRL1_PLLPD(pll) (0x04 << (pll)) argument
59 #define ADAV80X_PLL_CTRL2_FIELD(pll, x) ((x) << ((pll) * 4)) argument
61 #define ADAV80X_PLL_CTRL2_FS_48(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x00) argument
62 #define ADAV80X_PLL_CTRL2_FS_32(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x08) argument
63 #define ADAV80X_PLL_CTRL2_FS_44(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x0c) argument
[all …]
Dda9055.c1 // SPDX-License-Identifier: GPL-2.0-or-later
58 /* Input - Gain, Select and Filter Registers */
71 /* Output - Gain, Select and Filter Registers */
247 /* PLL divisor table */
288 0x0, 0x10, TLV_DB_SCALE_ITEM(-5400, 0, 0),
289 /* -54dB to 15dB */
290 0x11, 0x3f, TLV_DB_SCALE_ITEM(-5400, 150, 0)
295 /* -78dB to 12dB */
296 0x08, 0x7f, TLV_DB_SCALE_ITEM(-7800, 75, 0)
305 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -600, 600, 0);
[all …]
Dsrc4xxx.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright 2021-2022 Deqx Pty Ltd
25 static const DECLARE_TLV_DB_SCALE(src_tlv, -12750, 50, 0);
41 SOC_DAPM_ENUM("Port A source select", porta_out_src_enum);
43 SOC_DAPM_ENUM("Port B source select", portb_out_src_enum);
49 SOC_DAPM_ENUM("DIT source", dit_mux_enum);
55 SOC_DAPM_ENUM("SRC source select", src_in_enum);
68 SND_SOC_DAPM_MUX("Port A source",
75 SND_SOC_DAPM_MUX("Port B source",
98 SND_SOC_DAPM_MUX("SRC source", SND_SOC_NOPM, 0, 0, &src_in_control),
[all …]
Dwm8960.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8960.c -- WM8960 ALSA SoC Audio driver
5 * Copyright 2007-11 Wolfson Microelectronics, plc
29 /* R25 - Power 1 */
33 /* R26 - Power 2 */
38 /* R28 - Anti-pop 1 */
45 /* R29 - Anti-pop 2 */
51 static bool is_pll_freq_available(unsigned int source, unsigned int target);
192 if (wm8960->deemph) { in wm8960_set_deemph()
195 if (abs(deemph_settings[i] - wm8960->lrclk) < in wm8960_set_deemph()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/include/
Dbios_parser_types.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
197 /* Input: Signal Type - to be converted to Encoder mode */
207 /* Output: If non-zero, this refDiv value should be used to calculate
210 /* Output: If non-zero, this postDiv value should be used to calculate
218 enum controller_id controller_id; /* (Which CRTC uses this PLL) */
219 enum clock_source_id pll_id; /* Clock Source Id */
220 /* signal_type -> Encoder Mode - needed by VBIOS Exec table */
225 /* Calculated Reference divider of Display PLL */
227 /* Calculated Feedback divider of Display PLL */
229 /* Calculated Fractional Feedback divider of Display PLL */
[all …]
/linux-6.12.1/Documentation/userspace-api/media/mediactl/
Dmedia-types.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _media-controller-types:
10 .. _media-entity-functions:
11 .. _MEDIA-ENT-F-UNKNOWN:
12 .. _MEDIA-ENT-F-V4L2-SUBDEV-UNKNOWN:
13 .. _MEDIA-ENT-F-IO-V4L:
14 .. _MEDIA-ENT-F-IO-VBI:
15 .. _MEDIA-ENT-F-IO-SWRADIO:
16 .. _MEDIA-ENT-F-IO-DTV:
17 .. _MEDIA-ENT-F-DTV-DEMOD:
[all …]
/linux-6.12.1/include/dt-bindings/clock/
Dtegra186-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
419 * appropriate clock source, program the source rate and execute a
420 * specific sequence to switch to the new clock source for both memory
751 /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
809 …DQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */
813 /** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enab…
818 * @brief GPC2CLK-div-2
827 /** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
829 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */
831 /** Fixed 408MHz PLL for use by peripheral clocks */
[all …]
Dtegra234-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
66 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */
75 * appropriate clock source, program the source rate and execute a
76 * specific sequence to switch to the new clock source for both memory
196 /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
198 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain …
200 /** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
206 /** Fixed frequency 960MHz PLL for USB and EAVB */
382 /** @brief NAFLL clock source for BPMP */
[all …]
/linux-6.12.1/sound/soc/fsl/
Dfsl_utils.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
18 * fsl_asoc_get_dma_channel - determine the dma channel for a SSI node
42 return -EINVAL; in fsl_asoc_get_dma_channel()
44 if (!of_device_is_compatible(dma_channel_np, "fsl,ssi-dma-channel")) { in fsl_asoc_get_dma_channel()
46 return -EINVAL; in fsl_asoc_get_dma_channel()
55 * dai->platform name should already point to an allocated buffer. in fsl_asoc_get_dma_channel()
62 snprintf((char *)dai->platforms->name, DAI_NAME_SIZE, "%llx.%pOFn", in fsl_asoc_get_dma_channel()
65 iprop = of_get_property(dma_channel_np, "cell-index", NULL); in fsl_asoc_get_dma_channel()
68 return -EINVAL; in fsl_asoc_get_dma_channel()
[all …]
/linux-6.12.1/arch/arm/boot/dts/marvell/
Ddove-cubox.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
20 compatible = "gpio-leds";
21 pinctrl-0 = <&pmx_gpio_18>;
22 pinctrl-names = "default";
24 led-power {
27 default-state = "keep";
31 usb_power: regulator-1 {
32 compatible = "regulator-fixed";
33 regulator-name = "USB Power";
[all …]
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dsa8295p-adp.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
11 #include <dt-bindings/spmi/spmi.h>
12 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
15 #include "sa8540p-pmics.dtsi"
19 compatible = "qcom,sa8295p-adp", "qcom,sa8540p";
26 stdout-path = "serial0:115200n8";
29 dp2-connector {
[all …]
/linux-6.12.1/drivers/clk/imx/
Dclk-pllv1.c1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/clk-provider.h>
12 #define MFN_SIGN (BIT(MFN_BITS - 1))
13 #define MFN_MASK (MFN_SIGN - 1)
16 * struct clk_pllv1 - IMX PLLv1 clock descriptor
18 * @hw: clock source
19 * @base: base address of pll registers
22 * PLL clock version 1, found on i.MX1/21/25/27/31/35
32 static inline bool is_imx1_pllv1(struct clk_pllv1 *pll) in is_imx1_pllv1() argument
34 return pll->type == IMX_PLLV1_IMX1; in is_imx1_pllv1()
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