Lines Matching +full:pll +full:- +full:source

1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/clk-provider.h>
12 #define MFN_SIGN (BIT(MFN_BITS - 1))
13 #define MFN_MASK (MFN_SIGN - 1)
16 * struct clk_pllv1 - IMX PLLv1 clock descriptor
18 * @hw: clock source
19 * @base: base address of pll registers
22 * PLL clock version 1, found on i.MX1/21/25/27/31/35
32 static inline bool is_imx1_pllv1(struct clk_pllv1 *pll) in is_imx1_pllv1() argument
34 return pll->type == IMX_PLLV1_IMX1; in is_imx1_pllv1()
37 static inline bool is_imx21_pllv1(struct clk_pllv1 *pll) in is_imx21_pllv1() argument
39 return pll->type == IMX_PLLV1_IMX21; in is_imx21_pllv1()
42 static inline bool is_imx27_pllv1(struct clk_pllv1 *pll) in is_imx27_pllv1() argument
44 return pll->type == IMX_PLLV1_IMX27; in is_imx27_pllv1()
47 static inline bool mfn_is_negative(struct clk_pllv1 *pll, unsigned int mfn) in mfn_is_negative() argument
49 return !is_imx1_pllv1(pll) && !is_imx21_pllv1(pll) && (mfn & MFN_SIGN); in mfn_is_negative()
55 struct clk_pllv1 *pll = to_clk_pllv1(hw); in clk_pllv1_recalc_rate() local
62 reg = readl(pll->base); in clk_pllv1_recalc_rate()
65 * Get the resulting clock rate from a PLL register value and the input in clk_pllv1_recalc_rate()
70 * f = 2 * f_ref * -------------------- in clk_pllv1_recalc_rate()
88 if (mfn_is_negative(pll, mfn)) { in clk_pllv1_recalc_rate()
89 if (is_imx27_pllv1(pll)) in clk_pllv1_recalc_rate()
92 mfn_abs = BIT(MFN_BITS) - mfn; in clk_pllv1_recalc_rate()
102 if (mfn_is_negative(pll, mfn)) in clk_pllv1_recalc_rate()
103 ull = (rate * mfi) - ull; in clk_pllv1_recalc_rate()
117 struct clk_pllv1 *pll; in imx_clk_hw_pllv1() local
122 pll = kmalloc(sizeof(*pll), GFP_KERNEL); in imx_clk_hw_pllv1()
123 if (!pll) in imx_clk_hw_pllv1()
124 return ERR_PTR(-ENOMEM); in imx_clk_hw_pllv1()
126 pll->base = base; in imx_clk_hw_pllv1()
127 pll->type = type; in imx_clk_hw_pllv1()
135 pll->hw.init = &init; in imx_clk_hw_pllv1()
136 hw = &pll->hw; in imx_clk_hw_pllv1()
140 kfree(pll); in imx_clk_hw_pllv1()