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/linux-6.12.1/Documentation/devicetree/bindings/display/bridge/
Dfsl,imx8qxp-pixel-combiner.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-combiner.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qm/qxp Pixel Combiner
10 - Liu Ying <victor.liu@nxp.com>
13 The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
15 of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured as
16 either one screen, two screens, or virtual screens. The pixel combiner is
17 also responsible for generating some of the control signals for the pixel link
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Dfsl,imx8qxp-pixel-link.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qm/qxp Display Pixel Link
10 - Liu Ying <victor.liu@nxp.com>
13 The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
14 asynchronous linkage between pixel sources(display controller or
15 camera module) and pixel consumers(imaging or displays).
16 It consists of two distinct functions, a pixel transfer function and a
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/linux-6.12.1/drivers/gpu/drm/bridge/imx/
DKconfig7 tristate "Freescale i.MX8MP HDMI-TX bridge support"
32 Freescale i.MX8qm processor. Official name of LDB is pixel mapper.
42 Freescale i.MX8qxp processor. Official name of LDB is pixel mapper.
45 tristate "Freescale i.MX8QM/QXP pixel combiner"
50 Choose this to enable pixel combiner found in
54 tristate "Freescale i.MX8QM/QXP display pixel link"
59 Choose this to enable display pixel link found in
63 tristate "Freescale i.MX8QXP pixel link to display pixel interface"
67 Choose this to enable pixel link to display pixel interface(PXL2DPI)
Dimx8qxp-pixel-combiner.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <linux/media-bus-format.h>
52 #define DRIVER_NAME "imx8qxp-pixel-combiner"
78 return readl(pc->base + offset); in imx8qxp_pc_read()
84 writel(value, pc->base + offset); in imx8qxp_pc_write()
104 if (mode->hdisplay > 2560) in imx8qxp_pc_bridge_mode_valid()
113 struct imx8qxp_pc_channel *ch = bridge->driver_private; in imx8qxp_pc_bridge_attach()
114 struct imx8qxp_pc *pc = ch->pc; in imx8qxp_pc_bridge_attach()
117 DRM_DEV_ERROR(pc->dev, in imx8qxp_pc_bridge_attach()
119 return -EINVAL; in imx8qxp_pc_bridge_attach()
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DMakefile1 obj-$(CONFIG_DRM_IMX_LDB_HELPER) += imx-ldb-helper.o
2 obj-$(CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE) += imx8mp-hdmi-tx.o
3 obj-$(CONFIG_DRM_IMX8MP_HDMI_PVI) += imx8mp-hdmi-pvi.o
4 obj-$(CONFIG_DRM_IMX8QM_LDB) += imx8qm-ldb.o
5 obj-$(CONFIG_DRM_IMX8QXP_LDB) += imx8qxp-ldb.o
6 obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
7 obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
8 obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o
9 obj-$(CONFIG_DRM_IMX93_MIPI_DSI) += imx93-mipi-dsi.o
/linux-6.12.1/Documentation/gpu/amdgpu/display/
Ddc-glossary.rst7 'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere,
19 Application-Specific Integrated Circuit
31 Bits Per Pixel
34 * PCLK: Pixel Clock
41 * PPLL: Pixel PLL
49 Cathode Ray Tube Controller - commonly called "Controller" - Generates
50 raw stream of pixels, clocked at pixel clock
95 Display Stream Compression (Reduce the amount of bits to represent pixel
96 count while at the same pixel clock)
108 Display Micro-Controller Unit
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Ddcn-overview.rst10 .. kernel-figure:: dc_pipeline_overview.svg
19 * **Display Pipe and Plane (DPP)**: This block provides pre-blend pixel
20 processing such as color space conversion, linearization of pixel data, tone
24 multiple planes, using global or per-pixel alpha.
26 * **Output Pixel Processing (OPP)**: Process and format pixels to be sent to
29 * **Output Pipe Timing Combiner (OPTC)**: It generates time output to combine
38 * **Multi-Media HUB (MMHUBBUB)**: Memory controller interface for DMCUB and DWB
43 the Display Micro-Controller Unit - version B (DMCUB), which is handled via
66 1. Pixel data interface (red): Represents the pixel data flow;
84 ----------------------
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/inc/hw/
Dmpc.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
29 * Multiple Pipe/Plane Combiner (MPC) is a component in the hardware pipeline
30 * that performs blending of multiple planes, using global and per-pixel alpha.
31 * It also performs post-blending color correction operations according to the
36 * supporting "M MPC inputs -> N MPC outputs" flexible composition
39 * - Programmable blending structure to allow software controlled blending and
41 * - Programmable window location of each DPP in active region of display;
42 * - Combining multiple DPP pipes in one active region when a single DPP pipe
44 * - Combining multiple DPP from different SLS with blending;
45 * - Stereo formats from single DPP in top-bottom or side-by-side modes;
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/linux-6.12.1/Documentation/admin-guide/media/
Dimx.rst1 .. SPDX-License-Identifier: GPL-2.0
7 ------------
15 - Image DMA Controller (IDMAC)
16 - Camera Serial Interface (CSI)
17 - Image Converter (IC)
18 - Sensor Multi-FIFO Controller (SMFC)
19 - Image Rotator (IRT)
20 - Video De-Interlacing or Combining Block (VDIC)
25 image flip, 8x8 block transfer (see IRT description), pixel component
26 re-ordering (for example UYVY to YUYV) within the same colorspace, and
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/
Ddc.h2 * Copyright 2012-2023 Advanced Micro Devices, Inc.
108 // for example, 1080p -> 8K is 4.0, or 4000 raw value
116 // for example, 8K -> 1080p is 0.25, or 250 raw value
128 * DOC: color-management-caps
133 * abstracted HW. DCE 5-12 had almost no important changes, but starting with
140 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
156 * struct dpp_color_caps - color pipeline capabilities for display pipe and
161 * just plain 256-entry lookup
170 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes
171 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT
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/linux-6.12.1/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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