display/dc/dc.h

2  * Copyright 2012-2023 Advanced Micro Devices, Inc.
108 	// for example, 1080p -> 8K is 4.0, or 4000 raw value
116 	// for example, 8K -> 1080p is 0.25, or 250 raw value
128  * DOC: color-management-caps
133  * abstracted HW. DCE 5-12 had almost no important changes, but starting with
140  * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
156  * struct dpp_color_caps - color pipeline capabilities for display pipe and
161  * just plain 256-entry lookup
170  * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes
171  * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT
172  * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
192  * struct mpc_color_caps - color pipeline capabilities for multiple pipe and
201  * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
213  * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks
377  * re-programming however do not affect bandwidth consumption or clock
380  * updates, viewport offset changes, recout size changes and pixel depth changes.
510 	INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams
511 	INGAME_FAMS_DISABLE, // disable in-game fams
512 	INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display
513 	INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR strategies
517  * enum pipe_split_policy - Pipe split strategy supported by DCN
525 	 * pipe in order to bring the best trade-off between performance and
557 	DCN_PWR_STATE_UNKNOWN = -1,
572  * struct dc_clocks - DC pipe clocks
643 		unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
644 				dm_get_timestamp(dc->ctx) : 0
647 		if (dc->debug.bw_val_profile.enable) \
648 			dc->debug.bw_val_profile.total_count++
651 		if (dc->debug.bw_val_profile.enable) { \
653 				voltage_level_tick = dm_get_timestamp(dc->ctx); \
654 			dc->debug.bw_val_profile.skip_ ## status ## _count++; \
658 		if (dc->debug.bw_val_profile.enable) \
659 			voltage_level_tick = dm_get_timestamp(dc->ctx)
662 		if (dc->debug.bw_val_profile.enable) \
663 			watermark_tick = dm_get_timestamp(dc->ctx)
666 		if (dc->debug.bw_val_profile.enable) { \
667 			end_tick = dm_get_timestamp(dc->ctx); \
668 			dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
669 			dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
671 				dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
672 				dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
714 		bool opp : 1;	   /* Output pixel processing */
715 		bool optc : 1;	   /* Output pipe timing combiner */
775  * 15-2: reserved
776  * 31-16: timeout in ms
849  * struct dc_debug_options - DC debug struct
960 	/* TODO - remove once tested */
1511 	 * Color Transformations for pre-blend MCM (Shaper, 3DLUT, 1DLUT)
1542  * struct dc_validation_set - Struct to store surface/stream associations for validation
1623  * return - minimum required timing bandwidth in kbps.
1632  * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
1705 	 * Pending allows link HWSS to differentiate PHY vs non-PHY pattern,
1709 	 * pending_test_pattern will be invalid or contain a non-PHY test pattern
1822  * @reason - Indicate which event triggers this detection. dc may customize
1824  * return false - if detection is not fully completed. This could happen when
1827  * link->connection_type == dc_connection_mst_branch when returning false).
1828  * return true - detection is completed, link has been fully updated with latest
1840  * @dc_link - link the remote sink will be added to.
1841  * @edid - byte array of EDID raw data.
1842  * @len - size of the edid in byte
1843  * @init_data -
1852  * @link - link the sink should be removed from
1853  * @sink - sink to be removed.
1867  * @type - dc_connection_single if connected, dc_connection_none otherwise.
1868  * return - false if an unexpected error occurs, true otherwise.
1879  * return - true HPD is asserted (HPD high), false otherwise (HPD low)
1889  * @link - The link the HPD pin is associated with.
1890  * @enable = true - enable hardware HPD filter. HPD event will only queued to irq
1897  * @enable = false - disable hardware HPD filter. HPD event will be queued
1904  * @link_index - index to a link with ddc in i2c mode
1905  * @cmd - i2c command structure
1906  * return - true if success, false otherwise.
1914  * @link_index - index to a link with ddc in i2c mode
1915  * @cmd - i2c command structure
1916  * return - true if success, false otherwise.
1924  * retries or handle error states. The reply is returned in the payload->reply
1926  * transferred,or -1 on a failure.
1943  * TODO - When defer_handling is true the function will have a different purpose.
1948  * true - Downstream port status changed. DM should call DC to do the
1950  * false - no change in Downstream port status. No further action required
1965  * return true - hpd rx irq should be handled.
1966  * return false - it is safe to ignore hpd rx irq event
1971  * @link - link the hpd irq data associated with
1972  * @hpd_irq_dpcd_data - input hpd irq data
1973  * return - true if hpd irq data indicates a link lost
1979  * @link - link where the hpd irq data should be read from
1980  * @irq_data - output hpd irq data
1981  * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data
1991  * TODO - in the future we should consider to expand link resume interface to
2006  * return - total effective link bandwidth in kbps.
2046  * interface i.e stream_update->dsc_config
2054  * @link - current detected link
2055  * @req_bw - requested bandwidth in kbps
2056  * @link_settings - returned most optimal link settings that can fit the
2058  * return - false if link can't support requested bandwidth, true if link
2074  * @link -  a link with DP RX connection
2075  * return - if stream is committed to this link with MST signal type, type of
2084  * @link - a link with DP RX connection
2085  * return - max dp link settings the link can enable.
2093  * @link - a link with DP RX connection
2094  * return - highest encoding format link supports.
2100  * @link - a link with dp connector signal type
2101  * return - true if connected, false otherwise
2105 /* Force DP lane settings update to main-link video signal and notify the change
2110  * @lt_settings - a container structure with desired hw_lane_settings
2117  * test or debugging purpose. The test pattern will remain until next un-plug.
2119  * @link - active link with DP signal output enabled.
2120  * @test_pattern - desired test pattern to output.
2122  * @test_pattern_color_space - for video test pattern choose a desired color
2124  * @p_link_settings - For PHY pattern choose a desired link settings
2125  * @p_custom_pattern - some test pattern will require a custom input to
2127  * @cust_pattern_size - size of the custom pattern input.
2152  * @link_settings - if not NULL, force preferred link settings to the link.
2153  * @lt_override - a set of override pointers. If any pointer is none NULL, dc
2165 /* return - true if FEC is supported with connected DP RX, false otherwise */
2170  * return - true if FEC should be enabled, false otherwise.
2181  * NOTE: this interface doesn't update dp main-link. Calling this function will
2182  * cause DP TX main-link and DP RX power states out of sync. DM has to restore
2185  * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power
2190 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite
2191  * current value read from extended receiver cap from 02200h - 0220Fh.
2209 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */
2255  * return - true if trace is initialized and has valid data. False dp trace
2276  * @in_detection - true to get link training end time stamp of last link
2284  * @in_detection - true to get link training count of last link
2298  * Send a request from DP-Tx requesting to allocate BW remotely after
2325  * Unplug => de-allocate bw
2348 /* Sink Interfaces - A sink corresponds to a display output device */
2353 	// 8 byte port ID -> ELD.PortID
2355 	// 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
2357 	// 2 byte product code -> ELD.ProductCode