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/linux-6.12.1/drivers/media/i2c/
Dccs-pll.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * drivers/media/i2c/ccs-pll.h
17 /* CSI-2 or CCP-2 */
22 /* op pix clock is for all lanes in total normally */
37 * struct ccs_pll_branch_fr - CCS PLL configuration (front)
39 * A single branch front-end of the CCS PLL tree.
41 * @pre_pll_clk_div: Pre-PLL clock divisor
43 * @pll_ip_clk_freq_hz: PLL input clock frequency
44 * @pll_op_clk_freq_hz: PLL output clock frequency
54 * struct ccs_pll_branch_bk - CCS PLL configuration (back)
[all …]
Daptina-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include "aptina-pll.h"
26 dev_dbg(dev, "PLL: ext clock %u pix clock %u\n", in aptina_pll_calculate()
27 pll->ext_clock, pll->pix_clock); in aptina_pll_calculate()
29 if (pll->ext_clock < limits->ext_clock_min || in aptina_pll_calculate()
30 pll->ext_clock > limits->ext_clock_max) { in aptina_pll_calculate()
31 dev_err(dev, "pll: invalid external clock frequency.\n"); in aptina_pll_calculate()
32 return -EINVAL; in aptina_pll_calculate()
35 if (pll->pix_clock == 0 || pll->pix_clock > limits->pix_clock_max) { in aptina_pll_calculate()
36 dev_err(dev, "pll: invalid pixel clock frequency.\n"); in aptina_pll_calculate()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/media/i2c/
Daptina,mt9p031.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Aptina 1/2.5-Inch 5Mp CMOS Digital Image Sensor
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 The Aptina MT9P031 is a 1/2.5-inch CMOS active pixel digital image sensor
15 simple two-wire serial interface.
20 - aptina,mt9p006
21 - aptina,mt9p031
22 - aptina,mt9p031m
[all …]
Dsony,imx258.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
12 description: |-
13 IMX258 is a diagonal 5.867mm (Type 1/3.06) 13 Mega-pixel CMOS active pixel
14 type stacked image sensor with a square pixel array of size 4208 x 3120. It
16 CSI-2. The sensor exists in two different models, a standard variant
17 (IMX258) and a variant with phase detection autofocus (IMX258-PDAF).
24 - sony,imx258
[all …]
Dovti,ov7251.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Omnivision OV7251 is a 1/7.5-Inch CMOS active pixel digital image sensor
15 - Todor Tomov <todor.too@gmail.com>
25 description: XCLK Input Clock
27 clock-names:
30 clock-frequency:
31 description: Frequency of the xclk clock in Hz.
33 vdda-supply:
[all …]
Dsony,imx214.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sony 1/3.06-Inch 13.13MP CMOS Digital Image Sensor
10 - Ricardo Ribalda <ribalda@kernel.org>
13 The Sony IMX214 is a 1/3.06-inch CMOS active pixel digital image sensor with
15 interface. Image data is sent through MIPI CSI-2, through 2 or 4 lanes at a
19 - $ref: /schemas/media/video-interface-devices.yaml#
27 - 0x10
28 - 0x1a
[all …]
Dsony,imx290.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sony IMX290 1/2.8-Inch CMOS Image Sensor
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 description: |-
14 The Sony IMX290 is a 1/2.8-Inch CMOS Solid-state image sensor with Square
15 Pixel, available in either mono or colour variants. It is programmable
16 through I2C and 4-wire interfaces.
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dfsl,plldig.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,plldig.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock
10 - Wen He <wen.he_1@nxp.com>
13 NXP LS1028A has a clock domain PXLCLK0 used for the Display output
15 which generate and offers pixel clocks to Display.
19 const: fsl,ls1028a-plldig
27 '#clock-cells':
[all …]
/linux-6.12.1/Documentation/admin-guide/media/
Dmgb4.rst1 .. SPDX-License-Identifier: GPL-2.0
7 ---------------
13 There are two types of parameters - global / PCI card related, found under
23 | 0 - No module present
24 | 1 - FPDL3
25 | 2 - GMSL
33 | 1 - FPDL3
34 | 2 - GMSL
42 PRODUCT-REVISION-SERIES-SERIAL
55 | 0 - single
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/display/
Dcirrus,clps711x-fb.txt4 - compatible: Shall contain "cirrus,ep7209-fb".
5 - reg : Physical base address and length of the controller's registers +
7 - clocks : phandle + clock specifier pair of the FB reference clock.
8 - display : phandle to a display node as described in
9 Documentation/devicetree/bindings/display/panel/display-timing.txt.
11 - bits-per-pixel: Bits per pixel.
12 - ac-prescale : LCD AC bias frequency. This frequency is the required
13 AC bias frequency for a given manufacturer's LCD plate.
14 - cmap-invert : Invert the color levels (Optional).
17 - lcd-supply: Regulator for LCD supply voltage.
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/display/panel/
Dpanel-mipi-dbi-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-mipi-dbi-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Noralf Trønnes <noralf@tronnes.org>
23 - Power:
24 - Vdd: Power supply for display module
25 Called power-supply in this binding.
26 - Vddi: Logic level supply for interface signals
27 Called io-supply in this binding.
[all …]
Dpanel-timing.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-timing.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Sam Ravnborg <sam@ravnborg.org>
20 +-------+----------+-------------------------------------+----------+
24 +-------+----------+-------------------------------------+----------+
28 +-------+----------#######################################----------+
33 |<----->|<-------->#<-------+--------------------------->#<-------->|
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/display/bridge/
Dsamsung,mipi-dsim.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Jagan Teki <jagan@amarulasolutions.com>
12 - Marek Szyprowski <m.szyprowski@samsung.com>
21 - enum:
22 - samsung,exynos3250-mipi-dsi
23 - samsung,exynos4210-mipi-dsi
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/inc/
Dclock_source.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
52 * Pixel Clock Parameters structure
54 * when calculating Pixel Clock Dividers for requested Pixel Clock
65 * Display Port HW De spread of Reference Clock related Parameters structure
70 /* Flag for HW De Spread enabled (if enabled SS on DP Reference Clock)*/
72 /* Average DP Reference clock (in KHz)*/
74 /* DP Reference clock SS percentage
77 /* DP Reference clock SS percentage divider */
82 /*> Requested Pixel Clock
85 /*> Requested Sym Clock (relevant only for display port)*/
[all …]
/linux-6.12.1/arch/arm/boot/dts/ti/omap/
Dlogicpd-torpedo-37xx-devkit.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 /dts-v1/;
6 #include "logicpd-torpedo-som.dtsi"
7 #include "omap-gpmc-smsc9221.dtsi"
8 #include "logicpd-torpedo-baseboard.dtsi"
12 compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3";
15 compatible = "regulator-fixed";
16 regulator-name = "vwl1271";
17 regulator-min-microvolt = <1800000>;
18 regulator-max-microvolt = <1800000>;
[all …]
/linux-6.12.1/arch/powerpc/platforms/85xx/
Dt1042rdb_diu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 /*DIU Pixel ClockCR offset in scfg*/
20 /* DIU Pixel Clock bits of the PIXCLKCR */
73 * t1042rdb_set_pixel_clock: program the DIU's clock
74 * @pixclock: pixel clock in ps (pico seconds)
84 scfg_np = of_find_compatible_node(NULL, NULL, "fsl,t1040-scfg"); in t1042rdb_set_pixel_clock()
99 /* Convert pixclock into frequency */ in t1042rdb_set_pixel_clock()
105 * 'pxclk' is the ratio of the platform clock to the pixel clock. in t1042rdb_set_pixel_clock()
107 * range of values is 2-255. in t1042rdb_set_pixel_clock()
112 /* Disable the pixel clock, and set it to non-inverted and no delay */ in t1042rdb_set_pixel_clock()
[all …]
Dp1022_rdk.c32 /* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
39 * p1022rdk_set_pixel_clock: program the DIU's clock
41 * @pixclock: the wavelength, in picoseconds, of the clock
52 guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts"); in p1022rdk_set_pixel_clock()
65 /* Convert pixclock from a wavelength to a frequency */ in p1022rdk_set_pixel_clock()
71 * 'pxclk' is the ratio of the platform clock to the pixel clock. in p1022rdk_set_pixel_clock()
73 * range of values is 2-255. in p1022rdk_set_pixel_clock()
78 /* Disable the pixel clock, and set it to non-inverted and no delay */ in p1022rdk_set_pixel_clock()
79 clrbits32(&guts->clkdvdr, in p1022rdk_set_pixel_clock()
82 /* Enable the clock and set the pxclk */ in p1022rdk_set_pixel_clock()
[all …]
/linux-6.12.1/drivers/staging/fbtft/
Dfb_ra8875.c1 // SPDX-License-Identifier: GPL-2.0+
26 fbtft_par_dbg_hex(DEBUG_WRITE, par, par->info->device, u8, buf, len, in write_spi()
29 if (!par->spi) { in write_spi()
30 dev_err(par->info->device, in write_spi()
31 "%s: par->spi is unexpectedly NULL\n", __func__); in write_spi()
32 return -1; in write_spi()
37 return spi_sync(par->spi, &m); in write_spi()
42 gpiod_set_value(par->gpio.dc, 1); in init_display()
44 par->fbtftops.reset(par); in init_display()
46 if ((par->info->var.xres == 320) && (par->info->var.yres == 240)) { in init_display()
[all …]
/linux-6.12.1/include/linux/platform_data/
Dvideo-pxafb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Author: Jean-Frederic Clere
15 * bits 0 - 3: for LCD panel type:
17 * STN - for passive matrix
18 * DSTN - for dual scan passive matrix
19 * TFT - for active matrix
21 * bits 4 - 9 : for bus width
22 * bits 10-17 : for AC Bias Pin Frequency
24 * bit 19 : for pixel clock edge
25 * bit 20 : for output pixel format when base is RGBT16
[all …]
/linux-6.12.1/Documentation/driver-api/media/
Dtx-rx.rst1 .. SPDX-License-Identifier: GPL-2.0
3 .. _transmitter-receiver:
5 Pixel data transmitter and receiver drivers
8 V4L2 supports various devices that transmit and receive pixel data. Examples of
10 CSI-2 receiver in an SoC.
13 ---------
17 MIPI CSI-2
20 CSI-2 is a data bus intended for transferring images from cameras to
28 The parallel and `BT.656`_ buses transport one bit of data on each clock cycle
32 .. _`BT.656`: https://en.wikipedia.org/wiki/ITU-R_BT.656
[all …]
/linux-6.12.1/include/media/i2c/
Dmt9p031.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * struct mt9p031_platform_data - MT9P031 platform data
9 * @ext_freq: Input clock frequency
10 * @target_freq: Pixel clock frequency
/linux-6.12.1/drivers/gpu/drm/tilcdc/
Dtilcdc_drv.h1 /* SPDX-License-Identifier: GPL-2.0-only */
29 /* Defaulting to pixel clock defined on AM335x */
46 struct clk *clk; /* functional clock */
54 * Pixel Clock will be restricted to some value as
64 /* Supported pixel formats */
90 /* Sub-module for display. Since we don't know at compile time what panels
123 /* AC Bias Pin Frequency */
132 /* Bits per pixel */
141 /* Invert pixel clock */
150 /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
/linux-6.12.1/arch/arm/mach-sa1100/include/mach/
DSA-1100.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * FILE SA-1100.h
9 * System StrongARM SA-1100
12 * SA-1100 microprocessor (Advanced RISC Machine (ARM)
14 * StrongARM SA-1100 data sheet version 2.2.
21 #error You must include hardware.h not SA-1100.h
91 * Controller (UDC) Control/Status register end-point 0
94 * Controller (UDC) Control/Status register end-point 1
97 * Controller (UDC) Control/Status register end-point 2
100 * Controller (UDC) Data register end-point 0
[all …]
/linux-6.12.1/drivers/gpu/drm/stm/
Dltdc.h1 /* SPDX-License-Identifier: GPL-2.0 */
20 const u32 *pix_fmt_hw; /* supported hw pixel formats */
21 const u32 *pix_fmt_drm; /* supported drm pixel formats */
22 int pix_fmt_nb; /* number of pixel format */
23 bool pix_fmt_flex; /* pixel format flexibility supported */
24 bool non_alpha_only_l1; /* non-native no-alpha formats on layer 1 */
25 int pad_max_freq_hz; /* max frequency supported by pad */
31 bool dynamic_zorder; /* dynamic z-order */
46 struct clk *pixel_clk; /* lcd pixel clock */
/linux-6.12.1/drivers/gpu/drm/sti/
Dsti_hdmi.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 #include <media/cec-notifier.h>
46 * @clk_pix: hdmi pixel clock
47 * @clk_tmds: hdmi tmds clock
48 * @clk_phy: hdmi phy clock
49 * @clk_audio: hdmi audio clock
60 * @audio_pdev: ASoC hdmi-codec platform device
100 * specific configuration for a given TMDS clock frequency range.
102 * @min_tmds_freq: Lower bound of TMDS clock frequency this entry applies to
103 * @max_tmds_freq: Upper bound of TMDS clock frequency this entry applies to

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