admin-guide/media/mgb4.rst

1 .. SPDX-License-Identifier: GPL-2.0
7 ---------------
13 There are two types of parameters - global / PCI card related, found under
23     | 0 - No module present
24     | 1 - FPDL3
25     | 2 - GMSL
33     | 1 - FPDL3
34     | 2 - GMSL
42         PRODUCT-REVISION-SERIES-SERIAL
55     | 0 - single
56     | 1 - dual (default)
61     | 0 - OLDI/JEIDA
62     | 1 - SPWG/VESA (default)
72     | 0 - unlocked
73     | 1 - locked
77     pixel clock is running and the DE signal is moving.
82     | 0 - not detected
83     | 1 - detected
103     | 0 - active low
104     | 1 - active high
105     | 2 - not available
113     | 0 - active low
114     | 1 - active high
115     | 2 - not available
133     Input pixel clock frequency in kHz.
139     a valid frequency here.*
142     Width of the HSYNC signal in PCLK clock ticks.
148     Width of the VSYNC signal in PCLK clock ticks.
155     valid pixel in the video line (marked by DE=1).
161     Number of PCLK pulses between the end of the last valid pixel in the video
169     line with the first valid pixel (marked by DE=1).
175     Number of video lines between the end of the last valid pixel line (marked
182     PLL frequency range of the OLDI input clock generator. The PLL frequency is
183     derived from the Pixel Clock Frequency (PCLK) and is equal to PCLK if
187     | 0 - PLL < 50MHz (default)
188     | 1 - PLL >= 50MHz
205     | 0 - input 0
206     | 1 - input 1
207     | 2 - v4l2 output 0
208     | 3 - v4l2 output 1
231     the limited output pixel clock steps, the card can not always generate
241     | 0 - active low (default)
242     | 1 - active high
247     | 0 - active low (default)
248     | 1 - active high
253     | 0 - active low
254     | 1 - active high (default)
257     Output pixel clock frequency. Allowed values are between 25000-190000(kHz)
258     and there is a non-linear stepping between two consecutive allowed
259     frequencies. The driver finds the nearest allowed frequency to the given
261     frequency set by the driver. The default frequency is 61150kHz.
274     valid pixel in the video line (marked by DE=1). The default value is 50.
277     Number of PCLK pulses between the end of the last valid pixel in the video
283     line with the first valid pixel (marked by DE=1). The default value is 31.
286     Number of video lines between the end of the last valid pixel line (marked
295     | 0 - auto (default)
296     | 1 - single
297     | 2 - dual
305     | 0 - auto (default)
306     | 1 - single
307     | 2 - dual
315     | 0 - 12Gb/s (default)
316     | 1 - 6Gb/s
317     | 2 - 3Gb/s
318     | 3 - 1.5Gb/s
321     The GMSL multi-stream contains up to four video streams. This parameter
323     zero-based index of the stream. The default stream id is 0.
331     | 0 - disabled
332     | 1 - enabled (default)
335 --------------
338  - mgb4-fw.X - FPGA firmware.
339  - mgb4-data.X - Factory settings, e.g. card serial number.
341 The *mgb4-fw* partition is writable and is used for FW updates, *mgb4-data* is
342 read-only. The *X* attached to the partition name represents the card number.
344 also have a third partition named *mgb4-flash* available in the system. This
349 --------------
357 	| bit 1 - trigger 1 pending
358 	| bit 2 - trigger 2 pending
359 	| bit 5 - trigger 1 level
360 	| bit 6 - trigger 2 level
370 (every mgb4 video frame has a timestamp with the same clock source).
374 buffer mode - the values do not represent valid data in such case.*