Lines Matching +full:pixel +full:- +full:clock +full:- +full:frequency

1 // SPDX-License-Identifier: GPL-2.0-or-later
17 /*DIU Pixel ClockCR offset in scfg*/
20 /* DIU Pixel Clock bits of the PIXCLKCR */
73  * t1042rdb_set_pixel_clock: program the DIU's clock
74  * @pixclock: pixel clock in ps (pico seconds)
84 	scfg_np = of_find_compatible_node(NULL, NULL, "fsl,t1040-scfg");  in t1042rdb_set_pixel_clock()
99 	/* Convert pixclock into frequency */  in t1042rdb_set_pixel_clock()
105 	 * 'pxclk' is the ratio of the platform clock to the pixel clock.  in t1042rdb_set_pixel_clock()
107 	 * range of values is 2-255.  in t1042rdb_set_pixel_clock()
112 	/* Disable the pixel clock, and set it to non-inverted and no delay */  in t1042rdb_set_pixel_clock()
116 	/* Enable the clock and set the pxclk */  in t1042rdb_set_pixel_clock()
133 		return FSL_DIU_PORT_DVI; /* Dual-link LVDS is not supported */  in t1042rdb_valid_monitor_port()
139 	cpld_node = of_find_compatible_node(NULL, NULL, "fsl,t1042rdb-cpld");  in t1042rdb_diu_init()