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/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dqcom,pcie2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,pcie2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PCIe2 PHY controller
10 - Vinod Koul <vkoul@kernel.org>
13 The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
19 - const: qcom,qcs404-pcie2-phy
20 - const: qcom,pcie2-phy
24 - description: PHY register set
[all …]
Dtransmit-amplitude.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/transmit-amplitude.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common PHY and network PCS transmit amplitude property
10 Binding describing the peak-to-peak transmit amplitude for common PHYs
14 - Marek Behún <kabel@kernel.org>
17 tx-p2p-microvolt:
19 Transmit amplitude voltages in microvolts, peak-to-peak. If this property
20 contains multiple values for various PHY modes, the
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/linux-6.12.1/arch/arm/boot/dts/marvell/
Darmada-388-clearfog.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include "armada-388-clearfog.dtsi"
13 compatible = "solidrun,clearfog-pro-a1", "solidrun,clearfog-a1",
18 internal-regs {
28 reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
34 gpio-keys {
35 compatible = "gpio-keys";
36 pinctrl-0 = <&rear_button_pins>;
37 pinctrl-names = "default";
[all …]
Darmada-385-turris-omnia.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
8 * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
11 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/leds/common.h>
16 #include "armada-385.dtsi"
20 compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
23 stdout-path = &uart0;
[all …]
Darmada-385-linksys.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include "armada-385.dtsi"
18 stdout-path = "serial0:115200n8";
34 usb3_1_phy: usb3_1-phy {
35 compatible = "usb-nop-xceiv";
36 vcc-supply = <&usb3_1_vbus>;
37 #phy-cells = <0>;
40 usb3_1_vbus: usb3_1-vbus {
[all …]
Darmada-385-clearfog-gtr.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
9 SERDES mapping -
10 0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
12 2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
14 4. mini PCIe CON2 - PCIe2
15 5. SFP connector, or optionally SGMII Ethernet 1512 PHY
17 USB 2.0 mapping -
18 0. USB 2.0 - 0 USB pins header CON12
19 1. USB 2.0 - 1 mini PCIe CON2
[all …]
/linux-6.12.1/arch/arm64/boot/dts/marvell/
Dcn9130-cf.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
19 reg_usb3_vbus0: regulator-usb3-vbus0 {
20 compatible = "regulator-fixed";
21 regulator-name = "vbus0";
22 regulator-min-microvolt = <5000000>;
23 regulator-max-microvolt = <5000000>;
29 i2c-bus = <&cp0_i2c1>;
30 los-gpios = <&expander0 12 GPIO_ACTIVE_HIGH>;
31 mod-def0-gpios = <&expander0 15 GPIO_ACTIVE_LOW>;
[all …]
Darmada-8040-db.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include "armada-8040.dtsi"
13 compatible = "marvell,armada8040-db", "marvell,armada8040",
14 "marvell,armada-ap806-quad", "marvell,armada-ap806";
17 stdout-path = "serial0:115200n8";
34 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
35 compatible = "regulator-fixed";
36 regulator-name = "cp0-usb3h0-vbus";
37 regulator-min-microvolt = <5000000>;
[all …]
Darmada-7040-db.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include "armada-7040.dtsi"
13 compatible = "marvell,armada7040-db", "marvell,armada7040",
14 "marvell,armada-ap806-quad", "marvell,armada-ap806";
17 stdout-path = "serial0:115200n8";
31 cp0_exp_usb3_0_current_regulator: gpio-regulator {
32 compatible = "regulator-gpio";
33 regulator-name = "cp0-usb3-0-current-regulator";
34 regulator-type = "current";
[all …]
Darmada-7040-mochabin.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include "armada-7040.dtsi"
17 "marvell,armada-ap806-quad", "marvell,armada-ap806";
20 stdout-path = "serial0:115200n8";
34 sfp_eth0: sfp-eth0 {
36 i2c-bus = <&cp0_i2c1>;
37 los-gpios = <&sfp_gpio 3 GPIO_ACTIVE_HIGH>;
38 mod-def0-gpios = <&sfp_gpio 2 GPIO_ACTIVE_LOW>;
[all …]
Darmada-cp11x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
27 thermal-zones {
28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(ic-thermal) {
29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
42 cooling-maps { };
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/linux-6.12.1/arch/arm64/boot/dts/rockchip/
Drk3588-ok3588-c.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
4 #include "rk3588-fet3588-c.dtsi"
7 model = "Forlinx OK3588-C Board";
8 compatible = "forlinx,ok3588-c", "forlinx,fet3588-c", "rockchip,rk3588";
16 adc-keys-0 {
17 compatible = "adc-keys";
18 io-channels = <&saradc 0>;
19 io-channel-names = "buttons";
20 keyup-threshold-microvolt = <1800000>;
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Drk3588-edgeble-neu6a-io.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
10 stdout-path = "serial2:1500000n8";
13 vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
14 compatible = "regulator-fixed";
15 regulator-name = "vcc3v3_pcie2x1l0";
16 regulator-min-microvolt = <3300000>;
17 regulator-max-microvolt = <3300000>;
18 startup-delay-us = <5000>;
19 vin-supply = <&vcc_3v3_s3>;
[all …]
Drk3588-rock-5b.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
11 compatible = "radxa,rock-5b", "rockchip,rk3588";
20 stdout-path = "serial2:1500000n8";
23 analog-sound {
24 compatible = "audio-graph-card";
25 label = "rk3588-es8316";
35 hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
[all …]
Drk3588-turing-rk1.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Based on RK3588-EVB1 devicetree
11 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/pinctrl/rockchip.h>
24 fan: pwm-fan {
25 compatible = "pwm-fan";
26 cooling-levels = <0 25 95 145 195 255>;
27 fan-supply = <&vcc5v0_sys>;
28 pinctrl-names = "default";
[all …]
Drk3588s-khadas-edge2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/leds/common.h>
21 stdout-path = "serial2:1500000n8";
24 adc-keys {
25 compatible = "adc-keys";
26 io-channels = <&saradc 1>;
[all …]
Drk3588-friendlyelec-cm3588-nas.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/rockchip.h>
14 #include <dt-bindings/usb/pd.h>
15 #include "rk3588-friendlyelec-cm3588.dtsi"
19 compatible = "friendlyarm,cm3588-nas", "friendlyarm,cm3588", "rockchip,rk3588";
21 adc_key_recovery: adc-key-recovery {
22 compatible = "adc-keys";
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/linux-6.12.1/drivers/phy/qualcomm/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_ATH79_USB) += phy-ath79-usb.o
3 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
4 obj-$(CONFIG_PHY_QCOM_EDP) += phy-qcom-edp.o
5 obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
6 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
7 obj-$(CONFIG_PHY_QCOM_M31_USB) += phy-qcom-m31.o
8 obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o
10 obj-$(CONFIG_PHY_QCOM_QMP_COMBO) += phy-qcom-qmp-combo.o phy-qcom-qmp-usbc.o
11 obj-$(CONFIG_PHY_QCOM_QMP_PCIE) += phy-qcom-qmp-pcie.o
[all …]
Dphy-qcom-pcie2.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
7 #include <linux/clk-provider.h>
11 #include <linux/phy/phy.h>
16 #include <dt-bindings/phy/phy.h>
50 static int qcom_pcie2_phy_init(struct phy *phy) in qcom_pcie2_phy_init() argument
52 struct qcom_phy *qphy = phy_get_drvdata(phy); in qcom_pcie2_phy_init()
55 ret = reset_control_deassert(qphy->phy_reset); in qcom_pcie2_phy_init()
57 dev_err(qphy->dev, "cannot deassert pipe reset\n"); in qcom_pcie2_phy_init()
61 ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs); in qcom_pcie2_phy_init()
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/linux-6.12.1/arch/sh/drivers/pci/
Dpcie-sh7786.c1 // SPDX-License-Identifier: GPL-2.0
3 * Low-Level PCI Express Support for the SH7786
5 * Copyright (C) 2009 - 2011 Paul Mundt
15 #include <linux/dma-map-ops.h>
21 #include "pcie-sh7786.h"
46 .end = 0xfd000000 + SZ_8M - 1,
51 .end = 0xc0000000 + SZ_512M - 1,
56 .end = 0x10000000 + SZ_64M - 1,
61 .end = 0xfe100000 + SZ_1M - 1,
70 .end = 0xfd800000 + SZ_8M - 1,
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/linux-6.12.1/Documentation/devicetree/bindings/pci/
Dsnps,dw-pcie-ep.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
23 - compatible
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/linux-6.12.1/arch/arm/boot/dts/st/
Dspear1310.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
15 compatible = "st,spear-spics-gpio";
17 st-spics,peripcfg-reg = <0x3b0>;
18 st-spics,sw-enable-bit = <12>;
19 st-spics,cs-value-bit = <11>;
20 st-spics,cs-enable-mask = <3>;
21 st-spics,cs-enable-shift = <8>;
22 gpio-controller;
23 #gpio-cells = <2>;
27 compatible = "st,spear1310-miphy";
[all …]
/linux-6.12.1/arch/arm/boot/dts/broadcom/
Dbcm-ns.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
6 #include <dt-bindings/clock/bcm-nsp.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
[all …]
Dbcm-nsp.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-nsp.h>
38 #address-cells = <1>;
39 #size-cells = <1>;
42 interrupt-parent = <&gic>;
53 #address-cells = <1>;
54 #size-cells = <0>;
58 compatible = "arm,cortex-a9";
59 next-level-cache = <&L2>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/qcom/
Dqcom-ipq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
8 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
11 #include <dt-bindings/soc/qcom,gsbi.h>
[all …]

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