dts/st/spear1310.dtsi

1 // SPDX-License-Identifier: GPL-2.0-or-later
15 			compatible = "st,spear-spics-gpio";
17 			st-spics,peripcfg-reg = <0x3b0>;
18 			st-spics,sw-enable-bit = <12>;
19 			st-spics,cs-value-bit = <11>;
20 			st-spics,cs-enable-mask = <3>;
21 			st-spics,cs-enable-shift = <8>;
22 			gpio-controller;
23 			#gpio-cells = <2>;
27 			compatible = "st,spear1310-miphy";
30 			phy-id = <0>;
31 			#phy-cells = <1>;
36 			compatible = "st,spear1310-miphy";
39 			phy-id = <1>;
40 			#phy-cells = <1>;
45 			compatible = "st,spear1310-miphy";
48 			phy-id = <2>;
49 			#phy-cells = <1>;
54 			compatible = "snps,spear-ahci";
58 			phy-names = "sata-phy";
63 			compatible = "snps,spear-ahci";
67 			phy-names = "sata-phy";
72 			compatible = "snps,spear-ahci";
76 			phy-names = "sata-phy";
81 			compatible = "st,spear1340-pcie", "snps,dw-pcie";
83 			reg-names = "dbi", "config";
85 			num-lanes = <1>;
87 			phy-names = "pcie-phy";
88 			#address-cells = <3>;
89 			#size-cells = <2>;
92 				0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
93 			bus-range = <0x00 0xff>;
98 			compatible = "st,spear1340-pcie", "snps,dw-pcie";
100 			reg-names = "dbi", "config";
102 			num-lanes = <1>;
104 			phy-names = "pcie-phy";
105 			#address-cells = <3>;
106 			#size-cells = <2>;
109 				0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */
110 			bus-range = <0x00 0xff>;
114 		pcie2: pcie@b4000000 {  label
115 			compatible = "st,spear1340-pcie", "snps,dw-pcie";
117 			reg-names = "dbi", "config";
119 			num-lanes = <1>;
121 			phy-names = "pcie-phy";
122 			#address-cells = <3>;
123 			#size-cells = <2>;
126 				0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
127 			bus-range = <0x00 0xff>;
132 			compatible = "st,spear600-gmac";
135 			interrupt-names = "macirq";
136 			phy-mode = "mii";
141 			compatible = "st,spear600-gmac";
144 			interrupt-names = "macirq";
145 			phy-mode = "mii";
150 			compatible = "st,spear600-gmac";
153 			interrupt-names = "macirq";
154 			phy-mode = "rmii";
159 			compatible = "st,spear600-gmac";
162 			interrupt-names = "macirq";
163 			phy-mode = "rgmii";
168 			compatible = "st,spear1310-pinmux";
170 			#gpio-range-cells = <3>;
175 				#address-cells = <1>;
176 				#size-cells = <0>;
177 				compatible = "snps,designware-i2c";
184 				#address-cells = <1>;
185 				#size-cells = <0>;
186 				compatible = "snps,designware-i2c";
193 				#address-cells = <1>;
194 				#size-cells = <0>;
195 				compatible = "snps,designware-i2c";
202 				#address-cells = <1>;
203 				#size-cells = <0>;
204 				compatible = "snps,designware-i2c";
211 				#address-cells = <1>;
212 				#size-cells = <0>;
213 				compatible = "snps,designware-i2c";
220 				#address-cells = <1>;
221 				#size-cells = <0>;
222 				compatible = "snps,designware-i2c";
229 				#address-cells = <1>;
230 				#size-cells = <0>;
231 				compatible = "snps,designware-i2c";
241 				#address-cells = <1>;
242 				#size-cells = <0>;
282 				st,thermal-flags = <0x7000>;
286 				compatible = "st,spear-plgpio";
289 				#interrupt-cells = <1>;
290 				interrupt-controller;
291 				gpio-controller;
292 				#gpio-cells = <2>;
293 				gpio-ranges = <&pinmux 0 0 246>;
296 				st-plgpio,ngpio = <246>;
297 				st-plgpio,enb-reg = <0xd0>;
298 				st-plgpio,wdata-reg = <0x90>;
299 				st-plgpio,dir-reg = <0xb0>;
300 				st-plgpio,ie-reg = <0x30>;
301 				st-plgpio,rdata-reg = <0x70>;
302 				st-plgpio,mis-reg = <0x10>;
303 				st-plgpio,eit-reg = <0x50>;