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/linux-6.12.1/Documentation/devicetree/bindings/dma/
Dti-edma.txt3 The eDMA3 consists of two components: Channel controller (CC) and Transfer
4 Controller(s) (TC). The CC is the main entry for DMA users since it is
5 responsible for the DMA channel handling, while the TCs are responsible to
6 execute the actual DMA tansfer.
8 ------------------------------------------------------------------------------
9 eDMA3 Channel Controller
12 --------------------
13 - compatible: Should be:
14 - "ti,edma3-tpcc" for the channel controller(s) on OMAP,
16 - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
[all …]
Dti-dma-crossbar.txt1 Texas Instruments DMA Crossbar (DMA request router)
4 - compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
5 "ti,am335x-edma-crossbar" for AM335x and AM437x
6 - reg: Memory map for accessing module
7 - #dma-cells: Should be set to match with the DMA controller's dma-cells
8 for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar.
9 - dma-requests: Number of DMA requests the crossbar can receive
10 - dma-masters: phandle pointing to the DMA controller
12 The DMA controller node need to have the following poroperties:
13 - dma-requests: Number of DMA requests the controller can handle
[all …]
Dadi,axi-dmac.txt1 Analog Devices AXI-DMAC DMA controller
4 - compatible: Must be "adi,axi-dmac-1.00.a".
5 - reg: Specification for the controllers memory mapped register map.
6 - interrupts: Specification for the controllers interrupt.
7 - clocks: Phandle and specifier to the controllers AXI interface clock
8 - #dma-cells: Must be 1.
10 Required sub-nodes:
11 - adi,channels: This sub-node must contain a sub-node for each DMA channel. For
12 the channel sub-nodes the following bindings apply. They must match the
15 Required properties for adi,channels sub-node:
[all …]
/linux-6.12.1/drivers/dma/sh/
Drcar-dmac.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas R-Car Gen2/Gen3 DMA Controller Driver
5 * Copyright (C) 2014-2019 Renesas Electronics Inc.
11 #include <linux/dma-mapping.h>
28 * struct rcar_dmac_xfer_chunk - Descriptor for a hardware transfer
43 * struct rcar_dmac_hw_desc - Hardware descriptor for a transfer chunk
56 * struct rcar_dmac_desc - R-Car Gen2 DMA Transfer Descriptor
57 * @async_tx: base DMA asynchronous transaction descriptor
58 * @direction: direction of the DMA transfer
60 * @chcr: value of the channel configuration register for this transfer
[all …]
/linux-6.12.1/drivers/net/ipa/
Dgsi_trans.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2019-2024 Linaro Ltd.
9 #include <linux/dma-direction.h>
24 * A GSI transaction abstracts the behavior of a GSI channel by representing
28 * by the GSI transaction core, allowing users to simply describe operations
29 * to be performed. When a transaction has completed a callback function
30 * (dependent on the type of endpoint associated with the channel) allows
33 * To perform an operation (or set of them), a user of the GSI transaction
37 * exhaustion of the available TREs in a channel ring is detected as early
[all …]
/linux-6.12.1/drivers/dma/
Ddmaengine.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
7 * This code implements the DMA subsystem. It provides a HW-neutral interface
8 * for other kernel code to use asynchronous memory copy capabilities,
9 * if present, and allows different HW DMA drivers to register as providing
12 * Due to the fact we are accelerating what is already a relatively fast
13 * operation, the code goes to great lengths to avoid additional overhead,
21 * A subsystem can get access to a channel by calling dmaengine_get() followed
22 * by dma_find_channel(), or if it has need for an exclusive channel it can call
23 * dma_request_channel(). Once a channel is allocated a reference is taken
[all …]
/linux-6.12.1/drivers/gpio/
Dgpio-pcie-idio-24.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for the ACCES PCIe-IDIO-24 family
6 * This driver supports the following ACCES devices: PCIe-IDIO-24,
7 * PCIe-IDI-24, PCIe-IDO-24, and PCIe-IDIO-12.
43 * 18: DMA Channel 0 Interrupt Enable
44 * 19: DMA Channel 1 Interrupt Enable
46 * 21: DMA Channel 0 Interrupt Active
47 * 22: DMA Channel 1 Interrupt Active
48 * 23: Built-In Self-Test (BIST) Interrupt Active
50 * 25: DMA Channel 0 was the Bus Master during a Master or Target Abort
[all …]
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dsa8540p-ride.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include "sa8540p-pmics.dtsi"
17 compatible = "qcom,sa8540p-ride", "qcom,sa8540p";
29 stdout-path = "serial0:115200n8";
34 regulators-0 {
35 compatible = "qcom,pm8150-rpmh-regulators";
36 qcom,pmic-id = "a";
[all …]
Dsa8775p-ride.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
12 #include "sa8775p-pmics.dtsi"
28 stdout-path = "serial0:115200n8";
33 regulators-0 {
34 compatible = "qcom,pmm8654au-rpmh-regulators";
35 qcom,pmic-id = "a";
38 regulator-name = "vreg_s4a";
[all …]
/linux-6.12.1/arch/powerpc/boot/dts/
Dmpc8377_wlan.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2007-2009 Freescale Semiconductor Inc.
9 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
27 #address-cells = <1>;
28 #size-cells = <0>;
33 d-cache-line-size = <32>;
34 i-cache-line-size = <32>;
35 d-cache-size = <32768>;
[all …]
Dxpedite5200_xmon.dts1 // SPDX-License-Identifier: GPL-2.0-only
7 * xMon boot loader memory map which differs from U-Boot's.
10 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
17 form-factor = "PMC/XMC";
18 boot-bank = <0x0>;
33 #address-cells = <1>;
34 #size-cells = <0>;
39 d-cache-line-size = <32>; // 32 bytes
[all …]
Dmpc8377_rdb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
12 #address-cells = <1>;
13 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
32 d-cache-line-size = <32>;
33 i-cache-line-size = <32>;
34 d-cache-size = <32768>;
35 i-cache-size = <32768>;
[all …]
Dmpc8378_rdb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
12 #address-cells = <1>;
13 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
32 d-cache-line-size = <32>;
33 i-cache-line-size = <32>;
34 d-cache-size = <32768>;
35 i-cache-size = <32768>;
[all …]
Dmpc8315erdb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
12 #address-cells = <1>;
13 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
32 d-cache-line-size = <32>;
33 i-cache-line-size = <32>;
34 d-cache-size = <16384>;
35 i-cache-size = <16384>;
[all …]
Dxpedite5301.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "PMC/XMC";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>; // 32 bytes
35 i-cache-line-size = <32>; // 32 bytes
[all …]
Dxpedite5370.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 * XPedite5370 3U VPX single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
26 #address-cells = <1>;
27 #size-cells = <0>;
32 d-cache-line-size = <32>; // 32 bytes
33 i-cache-line-size = <32>; // 32 bytes
34 d-cache-size = <0x8000>; // L1, 32K
[all …]
Dcanyonlands.dts4 * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
[all …]
Dtqm8548-bigflash.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
[all …]
Dtqm8548.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
[all …]
/linux-6.12.1/include/linux/dma/
Dedma.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
30 * struct dw_edma_core_ops - platform-specific eDMA methods
31 * @irq_vector: Get IRQ number of the passed eDMA channel. Note the
32 * method accepts the channel id in the end-to-end
35 * @pci_address: Get PCIe bus address corresponding to the passed CPU
56 * enum dw_edma_chip_flags - Flags specific to an eDMA chip
64 * struct dw_edma_chip - representation of DesignWare eDMA controller hardware
67 * @nr_irqs: total number of DMA IRQs
68 * @ops DMA channel to IRQ number mapping
[all …]
/linux-6.12.1/arch/powerpc/boot/dts/fsl/
Dp1022si-post.dtsi14 * names of its contributors may be used to endorse or promote products
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
36 #address-cells = <2>;
37 #size-cells = <1>;
39 * The localbus on the P1022 is not a simple-bus because of the eLBC
42 compatible = "fsl,p1022-elbc", "fsl,elbc";
49 compatible = "fsl,mpc8548-pcie";
51 #size-cells = <2>;
52 #address-cells = <3>;
[all …]
/linux-6.12.1/drivers/rapidio/devices/
Drio_mport_cdev.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2014-2015 Integrated Device Technology, Inc.
7 * Copyright 2014-2015 Prodrive Technologies
8 * Andre van Herk <andre.van.herk@prodrive-technologies.com>
9 * Jerry Jacobs <jerry.jacobs@prodrive-technologies.com>
11 * Aurelien Jacquiot <a-jacquiot@ti.com>
32 #include <linux/dma-mapping.h>
56 DBG_DMA = BIT(4), /* DMA transfer messages */
82 MODULE_AUTHOR("Jerry Jacobs <jerry.jacobs@prodrive-technologies.com>");
83 MODULE_AUTHOR("Aurelien Jacquiot <a-jacquiot@ti.com>");
[all …]
/linux-6.12.1/include/soc/tegra/
Divc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
10 #include <linux/dma-mapping.h>
11 #include <linux/iosys-map.h>
20 struct iosys_map map; member
33 * tegra_ivc_read_get_next_frame - Peek at the next frame to receive
34 * @ivc pointer of the IVC channel
36 * Peek at the next frame to be received, without removing it from
39 * Returns a pointer to the frame, or an error encoded pointer.
41 int tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc, struct iosys_map *map);
44 * tegra_ivc_read_advance - Advance the read queue
[all …]
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dimx8mp-beacon-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
18 reg_wl_bt: regulator-wifi-bt {
19 compatible = "regulator-fixed";
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_reg_wl_bt>;
22 regulator-name = "wl-bt-pow-dwn";
23 regulator-min-microvolt = <3300000>;
24 regulator-max-microvolt = <3300000>;
26 startup-delay-us = <70000>;
27 regulator-always-on;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/dma/ti/
Dk3-bcdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 ---
6 $id: http://devicetree.org/schemas/dma/ti/k3-bcdma.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Peter Ujfalusi <peter.ujfalusi@gmail.com>
15 The Block Copy DMA (BCDMA) is intended to perform similar functions as the TR
16 mode channels of K3 UDMA-P.
19 Block copy channels mainly used for memory to memory transfers, but with
20 optional triggers a block copy channel can service peripherals by accessing
21 directly to memory mapped registers or area.
[all …]

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