bindings/dma/ti-edma.txt

3 The eDMA3 consists of two components: Channel controller (CC) and Transfer
4 Controller(s) (TC). The CC is the main entry for DMA users since it is
5 responsible for the DMA channel handling, while the TCs are responsible to
6 execute the actual DMA tansfer.
8 ------------------------------------------------------------------------------
9 eDMA3 Channel Controller
12 --------------------
13 - compatible:	Should be:
14 		- "ti,edma3-tpcc" for the channel controller(s) on OMAP,
16 		- "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
17 		  channel controller(s) on 66AK2G.
18 - #dma-cells:	Should be set to <2>. The first number is the DMA request
19 		number and the second is the TC the channel is serviced on.
20 - reg:		Memory map of eDMA CC
21 - reg-names:	"edma3_cc"
22 - interrupts:	Interrupt lines for CCINT, MPERR and CCERRINT.
23 - interrupt-names: "edma3_ccint", "edma3_mperr" and "edma3_ccerrint"
24 - ti,tptcs:	List of TPTCs associated with the eDMA in the following form:
27 SoC-specific Required properties:
28 --------------------------------
30 - ti,hwmods:	Name of the hwmods associated to the eDMA CC.
33 - power-domains:Should contain a phandle to a PM domain provider node
36 		Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
39 -------------------
40 - ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow
42 - ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by
43 		the driver, they are allocated to be used by for example the
45 - dma-channel-mask: Mask of usable channels.
48 		Documentation/devicetree/bindings/dma/dma-common.yaml
51 ------------------------------------------------------------------------------
55 --------------------
56 - compatible:	Should be:
57 		- "ti,edma3-tptc" for the transfer controller(s) on OMAP,
59 		- "ti,k2g-edma3-tptc", "ti,edma3-tptc" for the
61 - reg:		Memory map of eDMA TC
62 - interrupts:	Interrupt number for TCerrint.
64 SoC-specific Required properties:
65 --------------------------------
67 - ti,hwmods:	Name of the hwmods associated to the eDMA TC.
70 - power-domains:Should contain a phandle to a PM domain provider node
73 		Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
76 -------------------
77 - interrupt-names: "edma3_tcerrint"
79 ------------------------------------------------------------------------------
84 	compatible = "ti,edma3-tpcc";
87 	reg-names = "edma3_cc";
89 	interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint";
90 	dma-requests = <64>;
91 	#dma-cells = <2>;
95 	/* Channel 20 and 21 is allocated for memcpy */
96 	ti,edma-memcpy-channels = <20 21>;
97 	/* The following PaRAM slots are reserved: 35-44 and 100-109 */
98 	ti,edma-reserved-slot-ranges = <35 10>, <100 10>;
99 	/* The following channels are reserved: 35-44 */
100 	dma-channel-mask = <0xffffffff /* Channel 0-31 */
101 			    0xffffe007>; /* Channel 32-63 */
105 	compatible = "ti,edma3-tptc";
109 	interrupt-names = "edm3_tcerrint";
113 	compatible = "ti,edma3-tptc";
117 	interrupt-names = "edm3_tcerrint";
121 	compatible = "ti,edma3-tptc";
125 	interrupt-names = "edm3_tcerrint";
129 	compatible = "ti,omap4-sham";
133 	/* DMA channel 36 executed on eDMA TC0 - low priority queue */
135 	dma-names = "rx";
139 	compatible = "ti,am33xx-mcasp-audio";
143 	reg-names = "mpu", "dat";
145 	interrupt-names = "tx", "rx";
146 	/* DMA channels 8 and 9 executed on eDMA TC2 - high priority queue */
149 	dma-names = "tx", "rx";
154 	compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc";
156 	reg-names = "edma3_cc";
160 	interrupt-names = "edma3_ccint", "emda3_mperr",
162 	dma-requests = <64>;
163 	#dma-cells = <2>;
169 	 * ti,edma-memcpy-channels = <12 13 14 15>;
173 	power-domains = <&k2g_pds 0x4f>;
177 	compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
179 	power-domains = <&k2g_pds 0x4f>;
183 	compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
185 	power-domains = <&k2g_pds 0x4f>;
189 	compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc";
193 	dma-names = "tx", "rx";
194 	bus-width = <4>;
195 	ti,needs-special-reset;
196 	no-1-8-v;
197 	max-frequency = <96000000>;
198 	power-domains = <&k2g_pds 0xb>;
200 	clock-names = "fck", "mmchsdb_fck";
203 ------------------------------------------------------------------------------
204 DEPRECATED binding, new DTS files must use the ti,edma3-tpcc/ti,edma3-tptc
208 - compatible : "ti,edma3"
209 - #dma-cells: Should be set to <1>
210               Clients should use a single channel number per DMA request.
211 - reg: Memory map for accessing module
212 - interrupts: Exactly 3 interrupts need to be specified in the order:
217 - ti,hwmods: Name of the hwmods associated to the EDMA
218 - ti,edma-xbar-event-map: Crossbar event to channel map
221 Listed here in case one wants to boot an old kernel with new DTB. These
222 properties might need to be added to the new DTS files.
223 - ti,edma-regions: Number of regions
224 - ti,edma-slots: Number of slots
225 - dma-channels: Specify total DMA channels per CC
231 	interrupt-parent = <&intc>;
235 	#dma-cells = <1>;
236 	ti,edma-xbar-event-map = /bits/ 16 <1 12