Home
last modified time | relevance | path

Searched +full:jh7110 +full:- +full:dphy +full:- +full:tx (Results 1 – 9 of 9) sorted by relevance

/linux-6.12.1/drivers/phy/starfive/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
9 tristate "StarFive JH7110 D-PHY RX support"
14 Choose this option if you have a StarFive D-PHY in your
16 phy-jh7110-dphy-rx.ko.
19 tristate "StarFive JH7110 D-PHY TX Support"
24 Choose this option if you have a StarFive D-PHY TX in your
26 phy-jh7110-dphy-tx.ko.
29 tristate "Starfive JH7110 PCIE 2.0/USB 3.0 PHY support"
36 phy-jh7110-pcie.ko.
39 tristate "Starfive JH7110 USB 2.0 PHY support"
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_STARFIVE_JH7110_DPHY_RX) += phy-jh7110-dphy-rx.o
3 obj-$(CONFIG_PHY_STARFIVE_JH7110_DPHY_TX) += phy-jh7110-dphy-tx.o
4 obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE) += phy-jh7110-pcie.o
5 obj-$(CONFIG_PHY_STARFIVE_JH7110_USB) += phy-jh7110-usb.o
Dphy-jh7110-dphy-rx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * StarFive JH7110 DPHY RX driver
75 struct stf_dphy *dphy = phy_get_drvdata(phy); in stf_dphy_configure() local
76 const struct stf_dphy_info *info = dphy->info; in stf_dphy_configure()
84 FIELD_PREP(STF_DPHY_LANE_SWAP_CLK, info->maps[0]) | in stf_dphy_configure()
85 FIELD_PREP(STF_DPHY_LANE_SWAP_CLK1, info->maps[5]) | in stf_dphy_configure()
86 FIELD_PREP(STF_DPHY_LANE_SWAP_LAN0, info->maps[1]) | in stf_dphy_configure()
87 FIELD_PREP(STF_DPHY_LANE_SWAP_LAN1, info->maps[2]), in stf_dphy_configure()
88 dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(188)); in stf_dphy_configure()
90 writel(FIELD_PREP(STF_DPHY_LANE_SWAP_LAN2, info->maps[3]) | in stf_dphy_configure()
[all …]
Dphy-jh7110-dphy-tx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * DPHY TX driver for the StarFive JH7110 SoC
19 #include <linux/phy/phy-mipi-dphy.h>
212 static void stf_dphy_hw_reset(struct stf_dphy *dphy, int assert) in stf_dphy_hw_reset() argument
218 dphy->topsys + STF_DPHY_APBIFSAIF_SYSCFG(100)); in stf_dphy_hw_reset()
221 rc = readl_poll_timeout_atomic(dphy->topsys + in stf_dphy_hw_reset()
227 dev_err(dphy->dev, "MIPI dphy-tx # PLL Locked\n"); in stf_dphy_hw_reset()
233 struct stf_dphy *dphy = phy_get_drvdata(phy); in stf_dphy_configure() local
234 const struct stf_dphy_info *info = dphy->info; in stf_dphy_configure()
237 u32 bitrate = opts->mipi_dphy.hs_clk_rate; in stf_dphy_configure()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dstarfive,jh7110-dphy-tx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-tx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Starfive SoC MIPI D-PHY Tx Controller
10 - Keith Zhao <keith.zhao@starfivetech.com>
11 - Shengyang Chen <shengyang.chen@starfivetech.com>
14 The Starfive SoC uses the MIPI DSI D-PHY based on M31 IP to transfer
19 const: starfive,jh7110-dphy-tx
27 clock-names:
[all …]
Dstarfive,jh7110-dphy-rx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive SoC JH7110 MIPI D-PHY Rx Controller
10 - Jack Zhu <jack.zhu@starfivetech.com>
11 - Changhuang Liang <changhuang.liang@starfivetech.com>
14 StarFive SoCs contain a MIPI CSI D-PHY based on M31 IP, used to
19 const: starfive,jh7110-dphy-rx
26 - description: config clock
[all …]
/linux-6.12.1/arch/riscv/boot/dts/starfive/
Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "starfive,jh7110";
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
[all …]
/linux-6.12.1/drivers/pmdomain/starfive/
Djh71xx-pmu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
15 #include <dt-bindings/power/starfive,jh7110-pmu.h>
87 struct jh71xx_pmu *pmu = pmd->pmu; in jh71xx_pmu_get_state()
90 return -EINVAL; in jh71xx_pmu_get_state()
92 *is_on = readl(pmu->base + pmu->match_data->pmu_status) & mask; in jh71xx_pmu_get_state()
99 struct jh71xx_pmu *pmu = pmd->pmu; in jh7110_pmu_set_state()
107 spin_lock_irqsave(&pmu->lock, flags); in jh7110_pmu_set_state()
129 writel(mask, pmu->base + mode); in jh7110_pmu_set_state()
139 writel(JH71XX_PMU_SW_ENCOURAGE_ON, pmu->base + JH71XX_PMU_SW_ENCOURAGE); in jh7110_pmu_set_state()
[all …]
/linux-6.12.1/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
[all …]