Searched +full:irqc +full:- +full:rzg2l (Results 1 – 11 of 11) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>11 - Geert Uytterhoeven <geert+renesas@glider.be>15 interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral17 - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts18 - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts19 - NMI edge select (NMI is not treated as NMI exception and supports fall edge and[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/clock/r9a08g045-cpg.h>13 #address-cells = <2>;14 #size-cells = <2>;17 #address-cells = <1>;18 #size-cells = <0>;21 compatible = "arm,cortex-a55";24 #cooling-cells = <2>;25 next-level-cache = <&L3_CA55>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)8 #include <dt-bindings/interrupt-controller/arm-gic.h>16 #address-cells = <1>;17 #size-cells = <0>;20 compatible = "arm,cortex-a55";23 #cooling-cells = <2>;24 next-level-cache = <&L3_CA55>;25 enable-method = "psci";27 operating-points-v2 = <&cluster0_opp>;30 L3_CA55: cache-controller-0 {[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/interrupt-controller/irqc-rzg2l.h>10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>28 reg_1p8v: regulator-1p8v {29 compatible = "regulator-fixed";30 regulator-name = "fixed-1.8V";31 regulator-min-microvolt = <1800000>;32 regulator-max-microvolt = <1800000>;33 regulator-boot-on;[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/clock/r9a07g054-cpg.h>13 #address-cells = <2>;14 #size-cells = <2>;16 audio_clk1: audio1-clk {17 compatible = "fixed-clock";18 #clock-cells = <0>;20 clock-frequency = <0>;23 audio_clk2: audio2-clk {[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/clock/r9a07g044-cpg.h>13 #address-cells = <2>;14 #size-cells = <2>;16 audio_clk1: audio1-clk {17 compatible = "fixed-clock";18 #clock-cells = <0>;20 clock-frequency = <0>;23 audio_clk2: audio2-clk {[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/interrupt-controller/irqc-rzg2l.h>10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>38 reg_1p8v: regulator-1p8v {39 compatible = "regulator-fixed";40 regulator-name = "fixed-1.8V";41 regulator-min-microvolt = <1800000>;42 regulator-max-microvolt = <1800000>;43 regulator-boot-on;[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/interrupt-controller/irqc-rzg2l.h>10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>27 reg_1p8v: regulator-1p8v {28 compatible = "regulator-fixed";29 regulator-name = "fixed-1.8V";30 regulator-min-microvolt = <1800000>;31 regulator-max-microvolt = <1800000>;32 regulator-boot-on;[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)8 #include <dt-bindings/clock/r9a07g043-cpg.h>12 #address-cells = <2>;13 #size-cells = <2>;15 audio_clk1: audio1-clk {16 compatible = "fixed-clock";17 #clock-cells = <0>;19 clock-frequency = <0>;22 audio_clk2: audio2-clk {23 compatible = "fixed-clock";[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Renesas RZ/G2L IRQC Driver7 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>63 * struct rzg2l_irqc_reg_cache - registers cache (necessary for suspend/resume)73 * struct rzg2l_irqc_priv - IRQ controller private data structure90 return data->domain->host_data; in irq_data_to_priv()95 unsigned int hw_irq = hwirq - IRQC_IRQ_START; in rzg2l_clear_irq_int()99 iscr = readl_relaxed(priv->base + ISCR); in rzg2l_clear_irq_int()100 iitsr = readl_relaxed(priv->base + IITSR); in rzg2l_clear_irq_int()103 * ISCR can only be cleared if the type is falling-edge, rising-edge or in rzg2l_clear_irq_int()[all …]
1 # SPDX-License-Identifier: GPL-2.02 obj-$(CONFIG_IRQCHIP) += irqchip.o4 obj-$(CONFIG_AL_FIC) += irq-al-fic.o5 obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o6 obj-$(CONFIG_ATH79) += irq-ath79-cpu.o7 obj-$(CONFIG_ATH79) += irq-ath79-misc.o8 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o9 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o10 obj-$(CONFIG_ARCH_ACTIONS) += irq-owl-sirq.o11 obj-$(CONFIG_DAVINCI_CP_INTC) += irq-davinci-cp-intc.o[all …]