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/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/
Driscv,imsics.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Incoming MSI Controller (IMSIC)
10 - Anup Patel <anup@brainfault.org>
13 The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming
14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
15 AIA specification can be found at https://github.com/riscv/riscv-aia.
17 The IMSIC is a per-CPU (or per-HART) device with separate interrupt file
[all …]
/linux-6.12.1/Documentation/arch/sparc/oradax/
Ddax-hv-api.txt3 Publication date 2017-09-25 08:21
5 Extracted via "pdftotext -f 547 -l 572 -layout sun4v_20170925.pdf"
16 live-migration and other system management activities.
20 …high speed processoring of database-centric operations. The coprocessors may support one or more of
28 …e Completion Area and, unless execution order is specifically restricted through the use of serial-
32 …Guest software may implement a software timeout on CCB operations, and if the timeout is exceeded,…
33 …tion may be cancelled or killed via the ccb_kill API function. It is recommended for guest software
38 …There is no fixed limit on the number of outstanding CCBs guest software may have queued in the vi…
45 …device node in the guest MD (Section 8.24.17, “Database Analytics Accelerators (DAX) virtual-device
51 36.1.1.1. "ORCL,sun4v-dax" Device Compatibility
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/linux-6.12.1/Documentation/virt/kvm/devices/
Darm-vgic-v3.rst1 .. SPDX-License-Identifier: GPL-2.0
9 - KVM_DEV_TYPE_ARM_VGIC_V3 ARM Generic Interrupt Controller v3.0
12 will act as the VM interrupt controller, requiring emulated user-space devices
16 Creating a guest GICv3 device requires a host GICv3 as well.
23 KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
24 Base address in the guest physical address space of the GICv3 distributor
28 KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
29 Base address in the guest physical address space of the GICv3
35 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)
38 bits: | 63 .... 52 | 51 .... 16 | 15 - 12 |11 - 0
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/linux-6.12.1/arch/s390/mm/
Dgmap.c1 // SPDX-License-Identifier: GPL-2.0
3 * KVM guest address space mapping code
21 #include <asm/page-states.h>
41 * gmap_alloc - allocate and initialize a guest address space
44 * Returns a guest address space structure.
54 limit = _REGION3_SIZE - 1; in gmap_alloc()
58 limit = _REGION2_SIZE - 1; in gmap_alloc()
62 limit = _REGION1_SIZE - 1; in gmap_alloc()
66 limit = -1UL; in gmap_alloc()
73 INIT_LIST_HEAD(&gmap->crst_list); in gmap_alloc()
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/linux-6.12.1/tools/virtio/ringtest/
Dvirtio_ring_0_9.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Partial implementation of virtio 0.9. event index is used for signalling,
25 * (which skips index reads on consumer in favor of looking at
26 * high bits of ring id ^ 0x8000).
29 /* enabling the below activates experimental in-order code
41 struct guest { struct
51 unsigned char reserved[HOST_GUEST_PADDING - 10];
52 } guest; argument
55 /* we do not need to track last avail index
60 unsigned char reserved[HOST_GUEST_PADDING - 4];
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/linux-6.12.1/arch/x86/kvm/mmu/
Dpaging_tmpl.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
19 * The MMU needs to be able to access/walk 32-bit and 64-bit guest page tables,
20 * as well as guest EPT tables, so the code in this file is compiled thrice,
21 * once per guest PTE type. The per-type defines are #undef'd at the end.
50 (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
58 #define PT_HAVE_ACCESSED_DIRTY(mmu) (!(mmu)->cpu_role.base.ad_disabled)
64 /* Common logic, but per-type values. These also need to be undefined. */
98 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; in pse36_gfn_delta()
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/linux-6.12.1/Documentation/arch/powerpc/
Dpapr_hcalls.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Hypercall Op-codes (hcalls)
10 Virtualization on 64-bit Power Book3S Platforms is based on the PAPR
11 specification [1]_ which describes the run-time environment for a guest
15 - **IBM PowerVM (PHYP)**: IBM's proprietary hypervisor that supports AIX,
16 IBM-i and Linux as supported guests (termed as Logical Partitions
19 - **Qemu/KVM**: Supports PPC64 linux guests running on a PPC64 linux host.
22 On PPC64 arch a guest kernel running on top of a PAPR hypervisor is called
23 a *pSeries guest*. A pseries guest runs in a supervisor mode (HV=0) and must
28 Hence a Hypercall (hcall) is essentially a request by the pseries guest
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/linux-6.12.1/Documentation/virt/kvm/
Dapi.rst1 .. SPDX-License-Identifier: GPL-2.0
4 The Definitive KVM (Kernel-based Virtual Machine) API Documentation
13 - System ioctls: These query and set global attributes which affect the
17 - VM ioctls: These query and set attributes that affect an entire virtual
24 - vcpu ioctls: These query and set attributes that control the operation
32 - device ioctls: These query and set attributes that control the operation
49 task of actually running guest code.
80 facility that allows backward-compatible extensions to the API to be
104 the ioctl returns -ENOTTY.
122 -----------------------
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/linux-6.12.1/drivers/irqchip/
Dirq-riscv-imsic-state.c1 // SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "riscv-imsic: " fmt
22 #include "irq-riscv-imsic-state.h"
63 return imsic ? &imsic->global : NULL; in imsic_get_global_config()
74 imask = BIT(id & (__riscv_xlen - 1)); in __imsic_eix_read_clear()
102 * are XLEN-wide and we must not touch IDs which in __imsic_eix_update()
106 for (i = id & (__riscv_xlen - 1); id < last_id && i < __riscv_xlen; i++) { in __imsic_eix_update()
133 lockdep_assert_held(&lpriv->lock); in __imsic_local_sync()
135 for_each_set_bit(i, lpriv->dirty_bitmap, imsic->global.nr_ids + 1) { in __imsic_local_sync()
138 vec = &lpriv->vectors[i]; in __imsic_local_sync()
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Dirq-riscv-aplic-msi.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/irqchip/riscv-aplic.h>
13 #include <linux/irqchip/riscv-imsic.h>
21 #include "irq-riscv-aplic-main.h"
43 * The section "4.9.2 Special consideration for level-sensitive interrupt in aplic_msi_irq_retrigger_level()
44 * sources" of the RISC-V AIA specification says: in aplic_msi_irq_retrigger_level()
52 writel(d->hwirq, priv->regs + APLIC_SETIPNUM_LE); in aplic_msi_irq_retrigger_level()
60 * EOI handling is required only for level-triggered interrupts in aplic_msi_irq_eoi()
73 * Updating sourcecfg register for level-triggered interrupts in aplic_msi_irq_set_type()
84 struct aplic_msicfg *mc = &priv->msicfg; in aplic_msi_write_msg()
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/linux-6.12.1/arch/x86/kvm/
Dioapic.c7 * 75002 Paris - France
8 * http://www.linux-mandrake.com/
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
62 switch (ioapic->ioregsel) { in ioapic_read_indirect()
64 result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16) in ioapic_read_indirect()
70 result = ((ioapic->id & 0xf) << 24); in ioapic_read_indirect()
75 u32 redir_index = (ioapic->ioregsel - 0x10) >> 1; in ioapic_read_indirect()
79 u32 index = array_index_nospec( in ioapic_read_indirect() local
82 redir_content = ioapic->redirtbl[index].bits; in ioapic_read_indirect()
85 result = (ioapic->ioregsel & 0x1) ? in ioapic_read_indirect()
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Dpmu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine -- Performance Monitoring Unit support
39 /* Instruction-Accurate PDIR (PDIR++) */
51 * - Each perf counter is defined as "struct kvm_pmc";
52 * - There are two types of perf counters: general purpose (gp) and fixed.
56 * - pmu.c understands the difference between gp counters and fixed counters.
57 * However AMD doesn't support fixed-counters;
58 * - There are three types of index to access perf counters (PMC):
61 * MSR_F15H_PERF_CTRn, where MSR_F15H_PERF_CTR[0-3] are
63 * 2. MSR Index (named idx): This normally is used by RDPMC instruction.
[all …]
Dcpuid.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
66 /* Scattered Flag - For features that are scattered by cpufeatures.h. */
74 * Magic value used by KVM when querying userspace-provided CPUID entries and
75 * doesn't care about the CPIUD index because the index of the function in
77 * bit set in bits[63:32] and must be consumed as a u64 by cpuid_entry2_find()
78 * to avoid false positives when processing guest CPUID input.
80 #define KVM_CPUID_INDEX_NOT_SIGNIFICANT -1ull
83 struct kvm_cpuid_entry2 *entries, int nent, u32 function, u64 index) in cpuid_entry2_find() argument
89 * KVM has a semi-arbitrary rule that querying the guest's CPUID model in cpuid_entry2_find()
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Dpmu.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define vcpu_to_pmu(vcpu) (&(vcpu)->arch.pmu)
11 #define pmc_to_pmu(pmc) (&(pmc)->vcpu->arch.pmu)
16 /* retrieve the 4 bits for EN and PMI out of IA32_FIXED_CTR_CTRL */
58 * to/for the guest if the guest PMU supports at least "Architectural in kvm_pmu_has_perf_global_ctrl()
63 return pmu->version > 1; in kvm_pmu_has_perf_global_ctrl()
67 * KVM tracks all counters in 64-bit bitmaps, with general purpose counters
68 * mapped to bits 31:0 and fixed counters mapped to 63:32, e.g. fixed counter 0
69 * is tracked internally via index 32. On Intel, (AMD doesn't support fixed
71 * and similar MSRs, i.e. tracking fixed counters at base index 32 reduces the
[all …]
/linux-6.12.1/arch/x86/include/asm/
Dkvm_host.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Kernel-based Virtual Machine driver for Linux
31 #include <asm/pvclock-abi.h>
34 #include <asm/msr-index.h>
38 #include <asm/hyperv-tlfs.h>
81 /* x86-specific vcpu->requests bit members */
150 #define KVM_NR_PAGE_SIZES (KVM_MAX_HUGEPAGE_LEVEL - PG_LEVEL_4K + 1)
151 #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9)
154 #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1))
233 * DR6_ACTIVE_LOW combines fixed-1 and active-low bits.
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Dvmxfeatures.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Defines VMX CPU feature bits
8 #define NVMXINTS 5 /* N 32-bit words worth of info */
16 /* Pin-Based VM-Execution Controls, EPT/VPID, APIC and VM-Functions, word 0 */
17 #define VMX_FEATURE_INTR_EXITING ( 0*32+ 0) /* VM-Exit on vectored interrupts */
18 #define VMX_FEATURE_NMI_EXITING ( 0*32+ 3) /* VM-Exit on NMIs */
23 /* EPT/VPID features, scattered to bits 16-23 */
26 #define VMX_FEATURE_EPT_AD ( 0*32+ 18) /* "ept_ad" EPT Accessed/Dirty bits */
28 #define VMX_FEATURE_EPT_5LEVEL ( 0*32+ 20) /* "ept_5level" 5-level EPT paging */
30 /* Aggregated APIC features 24-27 */
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/linux-6.12.1/arch/x86/kvm/vmx/
Dpmu_intel.c1 // SPDX-License-Identifier: GPL-2.0-only
24 * Perf's "BASE" is wildly misleading, architectural PMUs use bits 31:16 of ECX
26 * further confuse things, non-architectural PMUs use bit 31 as a flag for
35 #define MSR_PMC_FULL_WIDTH_BIT (MSR_IA32_PMC0 - MSR_IA32_PERFCTR0)
40 u64 old_fixed_ctr_ctrl = pmu->fixed_ctr_ctrl; in reprogram_fixed_counters()
43 pmu->fixed_ctr_ctrl = data; in reprogram_fixed_counters()
44 for (i = 0; i < pmu->nr_arch_fixed_counters; i++) { in reprogram_fixed_counters()
53 __set_bit(KVM_FIXED_PMC_BASE_IDX + i, pmu->pmc_in_use); in reprogram_fixed_counters()
69 * non-architecturals PMUs (PMUs with version '0'). For architectural in intel_rdpmc_ecx_to_pmc()
70 * PMUs, bits 31:16 specify the PMC type and bits 15:0 specify the PMC in intel_rdpmc_ecx_to_pmc()
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/linux-6.12.1/drivers/gpu/drm/vboxvideo/
Dvboxvideo.h1 /* SPDX-License-Identifier: MIT */
2 /* Copyright (C) 2006-2016 Oracle Corporation */
10 * The last 4096 bytes of the guest VRAM contains the generic info for all
18 * Last 4096 bytes - Adapter information area.
20 * Slack - what left after dividing the VRAM.
24 * The Virtual Graphics Adapter information in the guest VRAM is stored by the
25 * guest video driver using structures prepended by VBOXVIDEOINFOHDR.
27 * When the guest driver writes dword 0 to the VBE_DISPI_INDEX_VBOX_VIDEO
30 * actual information chain. That way the guest driver can have some
40 * The guest driver writes dword 0xffffffff to the VBE_DISPI_INDEX_VBOX_VIDEO
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/linux-6.12.1/Documentation/arch/arm64/
Dperf.rst1 .. SPDX-License-Identifier: GPL-2.0
13 :Date: 2019-03-06
16 ------------
24 --------------
28 The kernel runs at EL2 with VHE and EL1 without. Guest kernels always run
34 For the guest this attribute will exclude EL1. Please note that EL2 is
35 never counted within a guest.
39 ----------
46 For a non-VHE host this attribute will exclude EL2 as we consider the
48 guest/host transitions.
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/linux-6.12.1/arch/mips/kvm/
Dvz.c44 * Number of guest VTLB entries to use, so we can catch inconsistency between
60 * First write with WG=1 to write upper bits, then write again in case in kvm_vz_write_gc0_ebase()
75 * These Config bits may be writable by the guest:
115 if (kvm_mips_guest_has_msa(&vcpu->arch)) in kvm_vz_config5_guest_wrmask()
119 * Permit guest FPU mode changes if FPU is enabled and the relevant in kvm_vz_config5_guest_wrmask()
122 if (kvm_mips_guest_has_fpu(&vcpu->arch)) { in kvm_vz_config5_guest_wrmask()
138 * VZ optionally allows these additional Config bits to be written by root:
140 * Config1: M, [MMUSize-1, C2, MD, PC, WR, CA], FP
158 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) in kvm_vz_config1_user_wrmask()
175 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) in kvm_vz_config3_user_wrmask()
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/linux-6.12.1/include/linux/irqchip/
Driscv-imsic.h1 /* SPDX-License-Identifier: GPL-2.0-only */
50 * XLEN-1 12 0
52 * -------------------------------------------------------------
53 * |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 |
54 * -------------------------------------------------------------
57 /* Bits representing Guest index, HART index, and Group index */
69 /* Number of guest interrupt identities */
72 /* Per-CPU IMSIC addresses */
/linux-6.12.1/arch/powerpc/include/asm/
Dkvm_host.h1 /* SPDX-License-Identifier: GPL-2.0-only */
28 #include <asm/guest-state-buffer.h>
43 * hardware supports). Both guest and host use this value.
59 /* PPC-specific vcpu->requests bit members */
78 /* Physical Address Mask - allowed range of real mode RAM access */
217 * which stores the guest's view of the second word of the HPTE
218 * (including the guest physical address of the mapping),
219 * plus forward and backward pointers in a doubly-linked ring
221 * ring are 32-bit HPTE indexes, to save space.
229 * The rmap array of size number of guest pages is allocated for each memslot.
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/linux-6.12.1/arch/riscv/include/asm/
Dkvm_aia.h1 /* SPDX-License-Identifier: GPL-2.0-only */
18 /* In-kernel irqchip created */
21 /* In-kernel irqchip initialized */
33 /* Number of group bits in IMSIC address */
36 /* Position of group bits in IMSIC address */
39 /* Number of hart bits in IMSIC address */
42 /* Number of guest bits in IMSIC address */
45 /* Guest physical address of APLIC */
63 /* CPU AIA CSR context of Guest VCPU */
66 /* CPU AIA CSR context upon Guest VCPU reset */
[all …]
/linux-6.12.1/include/xen/interface/
Dxen.h1 /* SPDX-License-Identifier: MIT */
5 * Guest OS interface to Xen.
69 /* Architecture-specific hypercall definitions. */
82 * Virtual interrupts that a guest OS may receive from Xen.
83 * In the side comments, 'V.' denotes a per-VCPU VIRQ while 'G.' denotes a
84 * global VIRQ. The former can be bound once per VCPU and cannot be re-bound.
85 * The latter can be allocated only once per guest: they must initially be
86 * allocated to VCPU0 but can subsequently be re-bound.
89 #define VIRQ_DEBUG 1 /* V. Request guest to dump debug info. */
102 /* Architecture-specific VIRQ definitions. */
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/linux-6.12.1/arch/powerpc/kvm/
De500.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All rights reserved.
13 * Copyright IBM Corp. 2007-2008
20 #include <asm/nohash/mmu-e500.h>
37 /* bits [6-5] MAS2_X1 and MAS2_X0 and [4-0] bits for WIMGE */
60 /* Unmodified copy of the guest's TLB -- shared with host userspace. */
66 /* KVM internal information associated with each guest TLB entry */
106 /* This geometry is the legacy default -- can be overridden by userspace */
114 #define tlbsel_of(index) ((index) >> 16) argument
115 #define esel_of(index) ((index) & 0xFFFF) argument
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