kvm/devices/arm-vgic-v3.rst

1 .. SPDX-License-Identifier: GPL-2.0
9   - KVM_DEV_TYPE_ARM_VGIC_V3     ARM Generic Interrupt Controller v3.0
12 will act as the VM interrupt controller, requiring emulated user-space devices
16 Creating a guest GICv3 device requires a host GICv3 as well.
23     KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
24       Base address in the guest physical address space of the GICv3 distributor
28     KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
29       Base address in the guest physical address space of the GICv3
35     KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)
38         bits:     | 63   ....  52  |  51   ....   16 | 15 - 12  |11 - 0
39         values:   |     count      |       base      |  flags   | index
41       - index encodes the unique redistributor region index
42       - flags: reserved for future use, currently 0
43       - base field encodes bits [51:16] of the guest physical base address
45       - count encodes the number of redistributors in the region. Must be
50       are filled with redistributors in the index order. The sum of all
53       index order, starting from index 0.
56       by presetting the index field in the attr data.
72     -E2BIG   Address outside of addressable IPA range
73     -EINVAL  Incorrectly aligned address, bad redistributor region
74              count/index, mixed redistributor region attribute usage
75     -EEXIST  Address already configured
76     -ENOENT  Attempt to read the characteristics of a non existing
78     -ENXIO   The group or attribute is unknown/unsupported for this device
80     -EFAULT  Invalid user pointer for attr->addr.
89       bits:     | 63   ....  32  |  31   ....    0 |
92     All distributor regs are (rw, 32-bit) and kvm_device_attr.addr points to a
93     __u32 value.  64-bit registers must be accessed by separately accessing the
96     Writes to read-only registers are ignored by the kernel.
124     way directly observable by the guest or userspace.  Userspace should read
135     registers simply sets the non-reserved bits to the value written.
142     This is identical to the value returned by a guest read from ISPENDR for an
145     because of an edge detected on the input line or because of a guest write
147     interrupt is activated or when the guest writes to ICPENDR. A level
149     high by a device, or because of a guest write to the ISPENDR register. Only
151     interrupt is no longer pending unless the guest also wrote to ISPENDR, and
157     interrupt activation, whereas the value returned by a guest read from
173     -ENXIO  Getting or setting this register is not yet supported
174     -EBUSY  One or more VCPUs are running
183       bits:     | 63      ....       32 | 31  ....  16 | 15  ....  0 |
194     (RES means the bits are reserved for future use and should be zero)::
199     All system regs accessed through this API are (rw, 64-bit) and
206     Error -ENXIO is returned when accessed in AArch32 mode.
211     -ENXIO   Getting or setting this register is not yet supported
212     -EBUSY   VCPU is running
213     -EINVAL  Invalid mpidr or register value supplied
228     -EINVAL  Value set is out of the expected range
229     -EBUSY   Value has already be set.
240       save all LPI pending bits into guest RAM pending tables.
247     -ENXIO   VGIC not properly configured as required prior to calling
249     -ENODEV  no online VCPU
250     -ENOMEM  memory shortage when allocating vgic internal data
251     -EFAULT  Invalid guest ram access
252     -EBUSY   One or more VCPUS are running
261       bits:     | 63      ....       32 | 31   ....    10 | 9  ....  0 |
281     supported, will be RAZ/WI.  LPIs are always edge-triggered and are
296     -EINVAL  vINTID is not multiple of 32 or info field is