arch/arm64/perf.rst

1 .. SPDX-License-Identifier: GPL-2.0
13 :Date: 2019-03-06
16 ------------
24 --------------
28 The kernel runs at EL2 with VHE and EL1 without. Guest kernels always run
34 For the guest this attribute will exclude EL1. Please note that EL2 is
35 never counted within a guest.
39 ----------
46 For a non-VHE host this attribute will exclude EL2 as we consider the
48 guest/host transitions.
50 For the guest this attribute has no effect. Please note that EL2 is
51 never counted within a guest.
55 ----------------------------
57 These attributes exclude the KVM host and guest, respectively.
59 The KVM host may run at EL0 (userspace), EL1 (non-VHE kernel) and EL2 (VHE
60 kernel or non-VHE hypervisor).
62 The KVM guest may run at EL0 (userspace) and EL1 (kernel).
65 exclusively rely on the PMU's hardware exception filtering - therefore we
66 must enable/disable counting on the entry and exit to the guest. This is
67 performed differently on VHE and non-VHE systems.
69 For non-VHE systems we exclude EL2 for exclude_host - upon entering and
70 exiting the guest we disable/enable the event as appropriate based on the
74 for exclude_host. Upon entering and exiting the guest we modify the event
79 non-VHE guest however please note that EL2 is never counted within a guest.
83 --------
85 On non-VHE hosts we enable/disable counters on the entry/exit of host/guest
86 transition at EL2 - however there is a period of time between
87 enabling/disabling the counters and entering/exiting the guest. We are
88 able to eliminate counters counting host events on the boundaries of guest
89 entry/exit when counting guest events by filtering out EL2 for
91 window at the guest entry/exit where host events are not captured.
99 --------
102 implementation is cpu-dependent.
106 This targets specifically self-monitoring tasks in order to reduce the overhead
109 How-to
110 ------
118 .. code-block:: sh
126 to the user the hardware counter's index and other necessary data. Using this
127 index enables the user to access the PMU registers using the `mrs` instruction.
133 and perf_evsel__read() functions. See `tools/lib/perf/tests/test-evsel.c`_ for
137 ---------------------------
143 Have a look at `tools/perf/arch/arm64/tests/user-events.c`_ for an example. It
147 .. code-block:: sh
149   perf test -v user
152 --------------------------------------
153 The user can request either a 32-bit (config1:0 == 0) or 64-bit (config1:0 == 1)
155 if a 64-bit counter is requested and the hardware doesn't support 64-bit
157 access. If a 32-bit counter is requested on hardware with 64-bit counters, then
158 userspace must treat the upper 32-bits read from the counter as UNKNOWN. The
160 and should be used to mask the upper bits as needed.
163 .. _tools/perf/arch/arm64/tests/user-events.c:
164 …rnel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/perf/arch/arm64/tests/user-events.c
165 .. _tools/lib/perf/tests/test-evsel.c:
166 …//git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/lib/perf/tests/test-evsel.c
172 --------
185 How-to
186 ------
190 .. list-table::
191    :header-rows: 1
193    * - Parameter
194      - Description
195    * - threshold
196      - Value to threshold the event by. A value of 0 means that
198    * - threshold_compare
199      - | Comparison function to use, with the following values supported:
201        | 0: Not-equal
203        | 2: Greater-than-or-equal
204        | 3: Less-than
205    * - threshold_count
206      - If this is set, count by 1 after passing the threshold condition
212 .. code-block:: sh
214   perf stat -e stall_slot/threshold=2,threshold_compare=2/ \
215             -e dtlb_walk/threshold=10,threshold_compare=3,threshold_count/
224 .. code-block:: sh
232 for threshold is limited to 12 bits, and the Perf tool will refuse to