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/linux-6.12.1/drivers/gpio/
Dgpio-en7523.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/gpio/driver.h>
15 * struct airoha_gpio_ctrl - Airoha GPIO driver data
34 static int airoha_dir_set(struct gpio_chip *gc, unsigned int gpio, in airoha_dir_set() argument
37 struct airoha_gpio_ctrl *ctrl = gc_to_ctrl(gc); in airoha_dir_set() local
38 u32 dir = ioread32(ctrl->dir[gpio / 16]); in airoha_dir_set()
39 u32 output = ioread32(ctrl->output); in airoha_dir_set()
40 u32 mask = BIT((gpio % 16) * 2); in airoha_dir_set()
44 output |= BIT(gpio); in airoha_dir_set()
47 output &= ~BIT(gpio); in airoha_dir_set()
[all …]
Dgpio-idt3243x.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/gpio/driver.h>
23 void __iomem *gpio; member
30 struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc); in idt_gpio_dispatch() local
37 pending = readl(ctrl->pic + IDT_PIC_IRQ_PEND); in idt_gpio_dispatch()
38 pending &= ~ctrl->mask_cache; in idt_gpio_dispatch()
39 for_each_set_bit(bit, &pending, gc->ngpio) { in idt_gpio_dispatch()
40 virq = irq_linear_revmap(gc->irq.domain, bit); in idt_gpio_dispatch()
51 struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc); in idt_gpio_irq_set_type() local
58 return -EINVAL; in idt_gpio_irq_set_type()
[all …]
Dgpio-realtek-otto.c1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <linux/gpio/driver.h>
29 /* Two bits per GPIO in IMR registers */
42 * realtek_gpio_ctrl - Realtek Otto GPIO driver data
45 * @base: Base address of the register block for a GPIO bank
49 * @bank_read: Read a bank setting as a single 32-bit value
50 * @bank_write: Write a bank setting as a single 32-bit value
53 * The DIR, DATA, and ISR registers consist of four 8-bit port values, packed
54 * into a single 32-bit register. Use @bank_read (@bank_write) to get (assign)
55 * a value from (to) these registers. The IMR register consists of four 16-bit
[all …]
Dgpio-ath79.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Atheros AR71XX/AR724X/AR913X GPIO API support
6 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
7 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
12 #include <linux/gpio/driver.h>
44 static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg) in ath79_gpio_read() argument
46 return readl(ctrl->base + reg); in ath79_gpio_read()
49 static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl, in ath79_gpio_write() argument
52 writel(val, ctrl->base + reg); in ath79_gpio_write()
56 struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits) in ath79_gpio_update_bits() argument
[all …]
Dgpio-omap.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support functions for OMAP GPIO
5 * Copyright (C) 2003-2005 Nokia Corporation
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
25 #include <linux/gpio/driver.h>
27 #include <linux/platform_data/gpio-omap.h>
36 u32 ctrl; member
78 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
84 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
109 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, in omap_set_gpio_direction() argument
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dcirrus,cs35l45.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
11 - Richard Fitzgerald <rf@opensource.cirrus.com>
18 - $ref: dai-common.yaml#
23 - cirrus,cs35l45
31 '#sound-dai-cells':
34 reset-gpios:
37 vdd-a-supply:
[all …]
/linux-6.12.1/drivers/net/mdio/
Dmdio-gpio.c1 // SPDX-License-Identifier: GPL-2.0
3 * GPIO based MDIO bitbang driver.
7 * by Laurent Pinchart <laurentp@cse-semaphore.com>
20 #include <linux/gpio/consumer.h>
22 #include <linux/mdio-bitbang.h>
23 #include <linux/mdio-gpio.h>
26 #include <linux/platform_data/mdio-gpio.h>
31 struct mdiobb_ctrl ctrl; member
38 bitbang->mdc = devm_gpiod_get_index(dev, NULL, MDIO_GPIO_MDC, in mdio_gpio_get_data()
40 if (IS_ERR(bitbang->mdc)) in mdio_gpio_get_data()
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/linux-6.12.1/arch/arm/boot/dts/marvell/
Dkirkwood-iomega_ix2_200.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include "kirkwood-6281.dtsi"
8 model = "Iomega StorCenter ix2-200";
9 compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood";
18 stdout-path = &uart0;
22 pinctrl: pin-controller@10000 {
23 pinctrl-0 = < &pmx_led_sata_brt_ctrl_1
33 pinctrl-names = "default";
35 pmx_button_reset: pmx-button-reset {
[all …]
Ddove.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/interrupt-controller/irq.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
12 interrupt-parent = <&intc>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "marvell,pj4a", "marvell,sheeva-v7";
27 next-level-cache = <&l2>;
[all …]
/linux-6.12.1/include/dt-bindings/sound/
Dcs35l45.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * cs35l45.h -- CS35L45 ALSA SoC audio driver DT bindings header
12 * cirrus,asp-sdout-hiz-ctrl
14 * TX_HIZ_UNUSED: TX pin high-impedance during unused slots.
15 * TX_HIZ_DISABLED: TX pin high-impedance when all channels disabled.
21 * Optional GPIOX Sub-nodes:
22 * The cs35l45 node can have up to three "cirrus,gpio-ctrlX" ('X' = [1,2,3])
23 * sub-nodes for configuring the GPIO pins.
25 * - gpio-dir : GPIO pin direction. Valid only when 'gpio-ctrl'
30 * - gpio-lvl : GPIO level. Valid only when 'gpio-ctrl' is 1 and 'gpio-dir' is 0.
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/iio/frequency/
Dadi,admfm2000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kim Seer Paller <kimseer.paller@analog.com>
22 - adi,admfm2000
24 '#address-cells':
27 '#size-cells':
31 "^channel@[0-1]$":
44 adi,mixer-mode:
52 switch-gpios:
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/iio/amplifiers/
Dadi,hmc425a.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
13 Digital Step Attenuator IIO devices with gpio interface.
15 ADRF5750 2 dB LSB, 4-Bit, Silicon Digital Attenuator, 10 MHz to 60 GHz
16 https://www.analog.com/media/en/technical-documentation/data-sheets/adrf5740.pdf
18 HMC425A 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL POSITIVE CONTROL ATTENUATOR, 2.2 - 8.0 GHz
19 https://www.analog.com/media/en/technical-documentation/data-sheets/hmc425A.pdf
21 HMC540S 1 dB LSB Silicon MMIC 4-Bit Digital Positive Control Attenuator, 0.1 - 8 GHz
[all …]
/linux-6.12.1/drivers/pinctrl/nuvoton/
Dpinctrl-ma35.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Shan-Chun Hung <schung@nuvoton.com>
13 #include <linux/gpio/driver.h>
24 #include "pinctrl-ma35.h"
33 /* GPIO control registers */
50 /* GPIO mode control */
59 /* GPIO pull-up and pull-down selection control */
66 * The MA35_GP_REG_INTEN bits 0 ~ 15 control low-level or falling edge trigger,
67 * while bits 16 ~ 31 control high-level or rising edge trigger.
84 /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/leds/
Dkinetic,ktd2692.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Markuss Broks <markuss.broks@gmail.com>
13 KTD2692 is the ideal power solution for high-power flash LEDs.
14 It uses ExpressWire single-wire programming for maximum flexibility.
16 The ExpressWire interface through CTRL pin can control LED on/off and
20 Also, When the AUX pin is pulled high while CTRL pin is high,
21 LED current will be ramped up to the flash-mode current level.
27 ctrl-gpios:
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/leds/backlight/
Dkinetic,ktd2801.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Kinetic Technologies KTD2801 one-wire backlight
10 - Duje Mihanović <duje.mihanovic@skole.hr>
14 by a single GPIO line. The driver can be controlled with a PWM signal
15 or by pulsing the GPIO line to set the backlight level. This is called
19 - $ref: common.yaml#
25 ctrl-gpios:
28 default-brightness: true
[all …]
/linux-6.12.1/arch/m68k/include/asm/
Dm525xsim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m525xsim.h -- ColdFire 525x System Integration Module support.
39 #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
42 #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
43 #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
44 #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
45 #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
46 #define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
47 #define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
48 #define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
[all …]
/linux-6.12.1/drivers/pinctrl/mvebu/
Dpinctrl-mvebu.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 * struct mvebu_mpp_ctrl_data - private data for the mpp ctrl operations
29 * struct mvebu_mpp_ctrl - describe a mpp control
35 * @mpp_gpio_req: (optional) special function to request gpio
36 * @mpp_gpio_dir: (optional) special function to set gpio direction
45 * to allow pin settings with varying gpio pins.
62 * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
63 * @val: ctrl setting value
64 * @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode
[all …]
/linux-6.12.1/drivers/staging/sm750fb/
Dddk750_power.c1 // SPDX-License-Identifier: GPL-2.0
34 unsigned int ctrl = 0; in sm750_set_power_mode() local
36 ctrl = peek32(POWER_MODE_CTRL) & ~POWER_MODE_CTRL_MODE_MASK; in sm750_set_power_mode()
43 ctrl |= POWER_MODE_CTRL_MODE_MODE0; in sm750_set_power_mode()
47 ctrl |= POWER_MODE_CTRL_MODE_MODE1; in sm750_set_power_mode()
51 ctrl |= POWER_MODE_CTRL_MODE_SLEEP; in sm750_set_power_mode()
60 ctrl &= ~POWER_MODE_CTRL_OSC_INPUT; in sm750_set_power_mode()
62 ctrl &= ~POWER_MODE_CTRL_336CLK; in sm750_set_power_mode()
65 ctrl |= POWER_MODE_CTRL_OSC_INPUT; in sm750_set_power_mode()
67 ctrl |= POWER_MODE_CTRL_336CLK; in sm750_set_power_mode()
[all …]
/linux-6.12.1/drivers/pinctrl/qcom/
Dpinctrl-lpass-lpi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
9 #include <linux/gpio/driver.h>
15 #include <linux/pinctrl/pinconf-generic.h>
19 #include "../pinctrl-utils.h"
21 #include "pinctrl-lpass-lpi.h"
29 struct pinctrl_dev *ctrl; member
44 return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); in lpi_gpio_read()
50 iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); in lpi_gpio_write()
67 return pctrl->data->nfunctions; in lpi_gpio_get_functions_count()
[all …]
Dpinctrl-ssbi-mpp.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/gpio/driver.h>
17 #include <linux/pinctrl/pinconf-generic.h>
22 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
25 #include "../pinctrl-utils.h"
90 * struct pm8xxx_pin_data - dynamic configuration for a pin
135 {"qcom,amux-route", PM8XXX_CONFIG_AMUX, 0},
136 {"qcom,analog-level", PM8XXX_CONFIG_ALEVEL, 0},
170 unsigned ctrl; in pm8xxx_mpp_update() local
175 switch (pin->mode) { in pm8xxx_mpp_update()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dbrcm,ns2-drd-phy.txt4 - compatible: brcm,ns2-drd-phy
5 - reg: offset and length of the NS2 PHY related registers.
6 - reg-names
8 icfg - for DRD ICFG configurations
9 rst-ctrl - for DRD IDM reset
10 crmu-ctrl - for CRMU core vdd, PHY and PHY PLL reset
11 usb2-strap - for port over current polarity reversal
12 - #phy-cells: Must be 0. No args required.
13 - vbus-gpios: vbus gpio binding
14 - id-gpios: id gpio binding
[all …]
/linux-6.12.1/drivers/media/pci/ivtv/
Divtv-gpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 gpio functions.
4 Merging GPIO support into driver:
6 Copyright (C) 2005-2007 Hans Verkuil <hverkuil@xs4all.nl>
10 #include "ivtv-driver.h"
11 #include "ivtv-cards.h"
12 #include "ivtv-gpio.h"
15 #include <media/v4l2-ctrls.h>
18 * GPIO assignment of Yuan MPG600/MPG160
41 * GPIO Initial Settings
[all …]
/linux-6.12.1/arch/arm/boot/dts/broadcom/
Dbcm7445.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #address-cells = <2>;
6 #size-cells = <2>;
9 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "brcm,brahma-b15";
22 enable-method = "brcm,brahma-b15";
27 compatible = "brcm,brahma-b15";
[all …]
/linux-6.12.1/drivers/platform/surface/aggregator/
Dcontroller.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2019-2022 Maximilian Luz <luzmaximilian@gmail.com>
11 #include <linux/gpio/consumer.h>
38 /* -- Safe counters. -------------------------------------------------------- */
41 * ssh_seq_reset() - Reset/initialize sequence ID counter.
46 WRITE_ONCE(c->value, 0); in ssh_seq_reset()
50 * ssh_seq_next() - Get next sequence ID.
57 u8 old = READ_ONCE(c->value); in ssh_seq_next()
61 while (unlikely((ret = cmpxchg(&c->value, old, new)) != old)) { in ssh_seq_next()
70 * ssh_rqid_reset() - Reset/initialize request ID counter.
[all …]
/linux-6.12.1/drivers/net/ethernet/freescale/fs_enet/
Dmii-bitbang.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <linux/mdio-bitbang.h>
28 struct mdiobb_ctrl ctrl; member
35 /* FIXME: If any other users of GPIO crop up, then these will have to
38 * bind the ports to a GPIO driver, and have this be a client of it.
55 static inline void mdio_dir(struct mdiobb_ctrl *ctrl, int dir) in mdio_dir() argument
57 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); in mdio_dir()
60 bb_set(bitbang->dir, bitbang->mdio_msk); in mdio_dir()
62 bb_clr(bitbang->dir, bitbang->mdio_msk); in mdio_dir()
65 in_be32(bitbang->dir); in mdio_dir()
[all …]

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